文件名称:V
介绍说明--下载内容均来自于网络,请自行研究使用
门禁系统设计:基本硬件包括门外键盘、数码管显示、电控门锁、门磁、关门键(由关门动作触发)、报警器、控制器、门内按键等。本文完成对控制器程序的编写,并对模块的功能进行仿真分析,最后通过仿真波形分析所设计系统的功能。
-Access Control System Design: Basic hardware including door keypad, digital display, electric door locks, door, close the door key (triggered by the closing action), alarms, controllers, door keys and so on. This complete procedures for the preparation of the controller, and module function simulation analysis, waveform analysis by simulation designed system.
-Access Control System Design: Basic hardware including door keypad, digital display, electric door locks, door, close the door key (triggered by the closing action), alarms, controllers, door keys and so on. This complete procedures for the preparation of the controller, and module function simulation analysis, waveform analysis by simulation designed system.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
V
.\LED_scan.vhd
.\VHDL.asm.rpt
.\VHDL.done
.\VHDL.fit.rpt
.\VHDL.fit.smsg
.\VHDL.fit.summary
.\VHDL.flow.rpt
.\VHDL.map.rpt
.\VHDL.map.summary
.\VHDL.pin
.\VHDL.qpf
.\VHDL.qsf
.\VHDL.qws
.\VHDL.sim.rpt
.\VHDL.tan.rpt
.\VHDL.tan.summary
.\VHDL.vhd
.\VHDL.vhd.bak
.\VHDL.vwf
.\alarm_count.vhd
.\count.vhd
.\count.vhd.bak
.\db
.\..\VHDL.asm.qmsg
.\..\VHDL.cbx.xml
.\..\VHDL.cmp.bpm
.\..\VHDL.cmp.cdb
.\..\VHDL.cmp.ecobp
.\..\VHDL.cmp.hdb
.\..\VHDL.cmp.kpt
.\..\VHDL.cmp.logdb
.\..\VHDL.cmp.rdb
.\..\VHDL.cmp.tdb
.\..\VHDL.cmp0.ddb
.\..\VHDL.cmp_merge.kpt
.\..\VHDL.db_info
.\..\VHDL.eco.cdb
.\..\VHDL.eds_overflow
.\..\VHDL.fit.qmsg
.\..\VHDL.hier_info
.\..\VHDL.hif
.\..\VHDL.lpc.html
.\..\VHDL.lpc.rdb
.\..\VHDL.lpc.txt
.\..\VHDL.map.bpm
.\..\VHDL.map.cdb
.\..\VHDL.map.ecobp
.\..\VHDL.map.hdb
.\..\VHDL.map.kpt
.\..\VHDL.map.logdb
.\..\VHDL.map.qmsg
.\..\VHDL.map_bb.cdb
.\..\VHDL.map_bb.hdb
.\..\VHDL.map_bb.logdb
.\..\VHDL.pre_map.cdb
.\..\VHDL.pre_map.hdb
.\..\VHDL.rpp.qmsg
.\..\VHDL.rtlv.hdb
.\..\VHDL.rtlv_sg.cdb
.\..\VHDL.rtlv_sg_swap.cdb
.\..\VHDL.sgate.rvd
.\..\VHDL.sgate_sm.rvd
.\..\VHDL.sgdiff.cdb
.\..\VHDL.sgdiff.hdb
.\..\VHDL.sim.cvwf
.\..\VHDL.sim.hdb
.\..\VHDL.sim.qmsg
.\..\VHDL.sim.rdb
.\..\VHDL.sld_design_entry.sci
.\..\VHDL.sld_design_entry_dsc.sci
.\..\VHDL.syn_hier_info
.\..\VHDL.tan.qmsg
.\..\VHDL.tis_db_list.ddb
.\..\VHDL.tmw_info
.\..\VHDL_global_asgn_op.abo
.\..\prev_cmp_VHDL.asm.qmsg
.\..\prev_cmp_VHDL.fit.qmsg
.\..\prev_cmp_VHDL.map.qmsg
.\..\prev_cmp_VHDL.qmsg
.\..\prev_cmp_VHDL.sim.qmsg
.\..\prev_cmp_VHDL.tan.qmsg
.\..\wed.wsf
.\decoder.vhd
.\door_contact.vhd
.\door_contact.vhd.bak
.\driver.vhd
.\incremental_db
.\..............\README
.\..............\compiled_partitions
.\..............\...................\VHDL.root_partition.cmp.atm
.\..............\...................\VHDL.root_partition.cmp.cfm
.\..............\...................\VHDL.root_partition.cmp.dfp
.\..............\...................\VHDL.root_partition.cmp.hdbx
.\..............\...................\VHDL.root_partition.cmp.kpt
.\..............\...................\VHDL.root_partition.cmp.logdb
.\..............\...................\VHDL.root_partition.cmp.rcf
.\..............\...................\VHDL.root_partition.map.atm
.\..............\...................\VHDL.root_partition.map.dpi
.\..............\...................\VHDL.root_partition.map.hdbx