文件名称:ADC_DualModeInterleaved
- 所属分类:
- 单片机(51,AVR,MSP430等)
- 资源属性:
- [C/C++] [源码]
- 上传时间:
- 2013-10-14
- 文件大小:
- 20kb
- 下载次数:
- 0次
- 提 供 者:
- ste***
- 相关连接:
- 无
- 下载说明:
- 别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容均来自于网络,请自行研究使用
stm32f4 adc 的代码,双通道,用DMA保存数据。-stm32f4 family c code, adc
This example provides a short descr iption of how to use the ADC peripheral to
convert a regular channel in Dual interleaved mode using DMA in mode 3 with 5Msps.
DMA mode 3 is used in interleaved mode in 6-bit and 8-bit resolutions.
The Dual interleaved delay is configured 6 ADC clk cycles.
On each DMA request (two data items are available) two bytes representing two
ADC-converted data items are transferred as a half word.
The data transfer order is similar to that of the DMA mode 2.
A DMA request is generated each time 2 data items are available
1st request: ADC_CDR[15:0] = (ADC2_DR[7:0] << 8) | ADC1_DR[7:0]
2nd request: ADC_CDR[15:0] = (ADC2_DR[7:0] << 8) | ADC1_DR[7:0]
The ADC1 and ADC2 are configured to convert ADC Channel 12, with conversion
triggered by software.
By this way, ADC channel 12 is converted each 6 cycles.
In this example, the system clock is 168MHz, APB2 =84MHz and ADC clock = APB2 /2.
Since ADCCLK=
This example provides a short descr iption of how to use the ADC peripheral to
convert a regular channel in Dual interleaved mode using DMA in mode 3 with 5Msps.
DMA mode 3 is used in interleaved mode in 6-bit and 8-bit resolutions.
The Dual interleaved delay is configured 6 ADC clk cycles.
On each DMA request (two data items are available) two bytes representing two
ADC-converted data items are transferred as a half word.
The data transfer order is similar to that of the DMA mode 2.
A DMA request is generated each time 2 data items are available
1st request: ADC_CDR[15:0] = (ADC2_DR[7:0] << 8) | ADC1_DR[7:0]
2nd request: ADC_CDR[15:0] = (ADC2_DR[7:0] << 8) | ADC1_DR[7:0]
The ADC1 and ADC2 are configured to convert ADC Channel 12, with conversion
triggered by software.
By this way, ADC channel 12 is converted each 6 cycles.
In this example, the system clock is 168MHz, APB2 =84MHz and ADC clock = APB2 /2.
Since ADCCLK=
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ADC_DualModeInterleaved\main.c
.......................\main.h
.......................\readme.txt
.......................\simulation.xls
.......................\stm32f4xx_conf.h
.......................\stm32f4xx_it.c
.......................\stm32f4xx_it.h
.......................\system_stm32f4xx.c
ADC_DualModeInterleaved