文件名称:Verilog_CLOCK-v2013.10.07
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介绍说明－－下载内容均来自于网络，请自行研究使用
六位数码管显示的电子钟，可以调整时间，通过验证-Six digital display electronic clock, you can adjust the time by verifying
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Verilog_CLOCK v2013.10.07\db\MyVerilogProject.ae.hdb
.........................\..\MyVerilogProject.asm.qmsg
.........................\..\MyVerilogProject.cbx.xml
.........................\..\MyVerilogProject.cmp.bpm
.........................\..\MyVerilogProject.cmp.cdb
.........................\..\MyVerilogProject.cmp.ecobp
.........................\..\MyVerilogProject.cmp.hdb
.........................\..\MyVerilogProject.cmp.kpt
.........................\..\MyVerilogProject.cmp.logdb
.........................\..\MyVerilogProject.cmp.rdb
.........................\..\MyVerilogProject.cmp.tdb
.........................\..\MyVerilogProject.cmp0.ddb
.........................\..\MyVerilogProject.cmp_merge.kpt
.........................\..\MyVerilogProject.db_info
.........................\..\MyVerilogProject.eco.cdb
.........................\..\MyVerilogProject.eda.qmsg
.........................\..\MyVerilogProject.fit.qmsg
.........................\..\MyVerilogProject.hier_info
.........................\..\MyVerilogProject.hif
.........................\..\MyVerilogProject.lpc.html
.........................\..\MyVerilogProject.lpc.rdb
.........................\..\MyVerilogProject.lpc.txt
.........................\..\MyVerilogProject.map.bpm
.........................\..\MyVerilogProject.map.cdb
.........................\..\MyVerilogProject.map.ecobp
.........................\..\MyVerilogProject.map.hdb
.........................\..\MyVerilogProject.map.kpt
.........................\..\MyVerilogProject.map.logdb
.........................\..\MyVerilogProject.map.qmsg
.........................\..\MyVerilogProject.map_bb.cdb
.........................\..\MyVerilogProject.map_bb.hdb
.........................\..\MyVerilogProject.map_bb.logdb
.........................\..\MyVerilogProject.merge.qmsg
.........................\..\MyVerilogProject.pre_map.cdb
.........................\..\MyVerilogProject.pre_map.hdb
.........................\..\MyVerilogProject.rpp.qmsg
.........................\..\MyVerilogProject.rtlv.hdb
.........................\..\MyVerilogProject.rtlv_sg.cdb
.........................\..\MyVerilogProject.rtlv_sg_swap.cdb
.........................\..\MyVerilogProject.sgate.rvd
.........................\..\MyVerilogProject.sgate_sm.rvd
.........................\..\MyVerilogProject.sgdiff.cdb
.........................\..\MyVerilogProject.sgdiff.hdb
.........................\..\MyVerilogProject.sld_design_entry.sci
.........................\..\MyVerilogProject.sld_design_entry_dsc.sci
.........................\..\MyVerilogProject.syn_hier_info
.........................\..\MyVerilogProject.tan.qmsg
.........................\..\MyVerilogProject.tis_db_list.ddb
.........................\..\MyVerilogProject.tmw_info
.........................\..\MyVerilogProject_global_asgn_op.abo
.........................\..\prev_cmp_MyVerilogProject.asm.qmsg
.........................\..\prev_cmp_MyVerilogProject.eda.qmsg
.........................\..\prev_cmp_MyVerilogProject.fit.qmsg
.........................\..\prev_cmp_MyVerilogProject.map.qmsg
.........................\..\prev_cmp_MyVerilogProject.merge.qmsg
.........................\..\prev_cmp_MyVerilogProject.qmsg
.........................\..\prev_cmp_MyVerilogProject.tan.qmsg
.........................\incremental_db\compiled_partitions\MyVerilogProject.root_partition.cmp.atm
.........................\..............\...................\MyVerilogProject.root_partition.cmp.dfp
.........................\..............\...................\MyVerilogProject.root_partition.cmp.hdbx
.........................\..............\...................\MyVerilogProject.root_partition.cmp.kpt
.........................\..............\...................\MyVerilogProject.root_partition.cmp.logdb
.........................\..............\...................\MyVerilogProject.root_partition.cmp.rcf
.........................\..............\...................\MyVerilogProject.root_partition.map.atm
.........................\..............\...................\MyVerilogProject.root_partition.map.dpi
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