文件名称:Chapter-4

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  • 2013-09-29
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4.1 二进制编码器bin_enc设计实例

4.2 曼彻斯特编译码器manch_ed设计实例

4.3 密勒译码器miller_de设计实例 

-4.1 binary encoder bin_enc Design Example 4.2 Manchester codec manch_ed Design Example 4.3 Miller decoder design example miller_de
(系统自动生成,下载前可以参看下载内容)

下载文件列表





Chapter-4\4.1\bin_enc.cr.mti

.........\...\bin_enc.mpf

.........\...\bin_enc.v

.........\...\bin_enc_testbench.v

.........\...\chart\Thumbs.db

.........\...\.....\图4-2.bmp

.........\...\.....\表4-1.bmp

.........\...\transcript

.........\...\vsim.wlf

.........\...\wave\bin_enc.bmp

.........\...\....\bin_enc_testbench.bmp

.........\...\....\Thumbs.db

.........\...\.ork\bin_enc\verilog.asm

.........\...\....\.......\_primary.dat

.........\...\....\.......\_primary.vhd

.........\...\....\......._testbench\verilog.asm

.........\...\....\.................\_primary.dat

.........\...\....\.................\_primary.vhd

.........\...\....\_info

.........\..2\chart\Thumbs.db

.........\...\.....\图4-5.bmp

.........\...\.....\图4-7.bmp

.........\...\manch_de.rpt

.........\...\manch_de.v

.........\...\manch_de_testbench.v

.........\...\manch_en.rpt

.........\...\manch_en.v

.........\...\manch_en_de.cr.mti

.........\...\manch_en_de.mpf

.........\...\manch_en_de.v

.........\...\manch_en_testbench.v

.........\...\transcript

.........\...\vsim.wlf

.........\...\wave\manch_de.bmp

.........\...\....\manch_de_testbench.bmp

.........\...\....\manch_en.bmp

.........\...\....\manch_en_testbench.bmp

.........\...\....\Thumbs.db

.........\...\.ork\manch_de\verilog.asm

.........\...\....\........\_primary.dat

.........\...\....\........\_primary.vhd

.........\...\....\........_testbench\verilog.asm

.........\...\....\..................\_primary.dat

.........\...\....\..................\_primary.vhd

.........\...\....\......en\verilog.asm

.........\...\....\........\_primary.dat

.........\...\....\........\_primary.vhd

.........\...\....\........_de\verilog.asm

.........\...\....\...........\_primary.dat

.........\...\....\...........\_primary.vhd

.........\...\....\.........testbench\verilog.asm

.........\...\....\..................\_primary.dat

.........\...\....\..................\_primary.vhd

.........\...\....\_info

.........\..3\chart\Thumbs.db

.........\...\.....\图4-11.bmp

.........\...\.....\图4-13.bmp

.........\...\decode.v

.........\...\decode_ter.rpt

.........\...\decode_testbench.v

.........\...\miller_de.cr.mti

.........\...\miller_de.mpf

.........\...\miller_de.v

.........\...\miller_de_testbench.v

.........\...\Signal_detect.v

.........\...\signal_detect_testbench.v

.........\...\signal_ter.rpt

.........\...\transcript

.........\...\vsim.wlf

.........\...\wave\decode.bmp

.........\...\....\decode_testbench.bmp

.........\...\....\miller_de.bmp

.........\...\....\miller_de_testbench.bmp

.........\...\....\signal_detect.bmp

.........\...\....\signal_detect_testbench.bmp

.........\...\....\Thumbs.db

.........\...\.ork\decode\verilog.asm

.........\...\....\......\_primary.dat

.........\...\....\......\_primary.vhd

.........\...\....\......_testbench\verilog.asm

.........\...\....\................\_primary.dat

.........\...\....\................\_primary.vhd

.........\...\....\miller_de\verilog.asm

.........\...\....\.........\_primary.dat

.........\...\....\.........\_primary.vhd

.........\...\....\........._testbench\verilog.asm

.........\...\....\...................\_primary.dat

.........\...\....\...................\_primary.vhd

.........\...\....\signal_detect\verilog.asm

.........\...\....\.............\_primary.dat

.........\...\....\.............\_primary.vhd

.........\...\....\............._testbench\verilog.asm

.........\...\....\.......................\_primary.dat

.........\...\....\.......................\_primary.vhd

.........\...\....\_info

.........\..1\work\bin_enc

.........\...\....\bin_enc_testbench

.........\..2\work\manch_de

.........\...\....\manch_de_testbench

.........\...\....\manch_en

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