文件名称:latch
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FPGA锁存器代码,EPM240上已经验证了,可以借鉴使用,用Verilog语言编写-FPGA latches code, EPM240 has been verified, you can learn to use, with the Verilog language
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下载文件列表
latch
.....\Project
.....\.......\db
.....\.......\..\latch.cbx.xml
.....\.......\..\latch.cmp.rdb
.....\.......\..\latch.dbp
.....\.......\..\latch.db_info
.....\.......\..\latch.eco.cdb
.....\.......\..\latch.hier_info
.....\.......\..\latch.hif
.....\.......\..\latch.map.bpm
.....\.......\..\latch.map.cdb
.....\.......\..\latch.map.ecobp
.....\.......\..\latch.map.hdb
.....\.......\..\latch.map.logdb
.....\.......\..\latch.map.qmsg
.....\.......\..\latch.map_bb.cdb
.....\.......\..\latch.map_bb.hdb
.....\.......\..\latch.map_bb.logdb
.....\.......\..\latch.pre_map.cdb
.....\.......\..\latch.pre_map.hdb
.....\.......\..\latch.psp
.....\.......\..\latch.pss
.....\.......\..\latch.rpp.qmsg
.....\.......\..\latch.rtlv.hdb
.....\.......\..\latch.rtlv_sg.cdb
.....\.......\..\latch.rtlv_sg_swap.cdb
.....\.......\..\latch.sgate.rvd
.....\.......\..\latch.sgate_sm.rvd
.....\.......\..\latch.sgdiff.cdb
.....\.......\..\latch.sgdiff.hdb
.....\.......\..\latch.sld_design_entry.sci
.....\.......\..\latch.sld_design_entry_dsc.sci
.....\.......\..\latch.syn_hier_info
.....\.......\..\latch.tis_db_list.ddb
.....\.......\..\prev_cmp_latch.map.qmsg
.....\.......\..\prev_cmp_latch.qmsg
.....\.......\latch.done
.....\.......\latch.flow.rpt
.....\.......\latch.map.rpt
.....\.......\latch.map.summary
.....\.......\latch.qpf
.....\.......\latch.qsf
.....\.......\latch.qws
.....\.......\RTL
.....\.......\...\latch.v
.....\.......\...\综合出来的电路.bmp
.....\详细设计方案
.....\............\详细设计文档—锁存器.doc