文件名称:top_module
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fpga 使用verilog hdl 语言，quartusii 9.0编程环境，设计的4个led灯分别实现不同功能，然后由一个顶层文件调用，完成总的设计。-fpga using verilog hdl language, quartusii 9.0 programming environment designed four different functions, respectively, led lights, followed by a top-level document called, completed a total design.
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下载文件列表
top_module\db\prev_cmp_top_module.asm.qmsg
..........\..\prev_cmp_top_module.fit.qmsg
..........\..\prev_cmp_top_module.map.qmsg
..........\..\prev_cmp_top_module.qmsg
..........\..\prev_cmp_top_module.tan.qmsg
..........\..\top_module.asm.qmsg
..........\..\top_module.asm_labs.ddb
..........\..\top_module.cbx.xml
..........\..\top_module.cmp.bpm
..........\..\top_module.cmp.cdb
..........\..\top_module.cmp.ecobp
..........\..\top_module.cmp.hdb
..........\..\top_module.cmp.kpt
..........\..\top_module.cmp.logdb
..........\..\top_module.cmp.rdb
..........\..\top_module.cmp.tdb
..........\..\top_module.cmp0.ddb
..........\..\top_module.cmp2.ddb
..........\..\top_module.cmp_merge.kpt
..........\..\top_module.db_info
..........\..\top_module.eco.cdb
..........\..\top_module.eds_overflow
..........\..\top_module.fit.qmsg
..........\..\top_module.hier_info
..........\..\top_module.hif
..........\..\top_module.lpc.html
..........\..\top_module.lpc.rdb
..........\..\top_module.lpc.txt
..........\..\top_module.map.bpm
..........\..\top_module.map.cdb
..........\..\top_module.map.ecobp
..........\..\top_module.map.hdb
..........\..\top_module.map.kpt
..........\..\top_module.map.logdb
..........\..\top_module.map.qmsg
..........\..\top_module.map_bb.cdb
..........\..\top_module.map_bb.hdb
..........\..\top_module.map_bb.logdb
..........\..\top_module.pre_map.cdb
..........\..\top_module.pre_map.hdb
..........\..\top_module.rpp.qmsg
..........\..\top_module.rtlv.hdb
..........\..\top_module.rtlv_sg.cdb
..........\..\top_module.rtlv_sg_swap.cdb
..........\..\top_module.sgate.rvd
..........\..\top_module.sgate_sm.rvd
..........\..\top_module.sgdiff.cdb
..........\..\top_module.sgdiff.hdb
..........\..\top_module.sim.cvwf
..........\..\top_module.sim.hdb
..........\..\top_module.sim.qmsg
..........\..\top_module.sim.rdb
..........\..\top_module.sld_design_entry.sci
..........\..\top_module.sld_design_entry_dsc.sci
..........\..\top_module.syn_hier_info
..........\..\top_module.tan.qmsg
..........\..\top_module.tis_db_list.ddb
..........\..\top_module_global_asgn_op.abo
..........\..\wed.wsf
..........\incremental_db\compiled_partitions\top_module.root_partition.cmp.atm
..........\..............\...................\top_module.root_partition.cmp.dfp
..........\..............\...................\top_module.root_partition.cmp.hdbx
..........\..............\...................\top_module.root_partition.cmp.kpt
..........\..............\...................\top_module.root_partition.cmp.logdb
..........\..............\...................\top_module.root_partition.cmp.rcf
..........\..............\...................\top_module.root_partition.map.atm
..........\..............\...................\top_module.root_partition.map.dpi
..........\..............\...................\top_module.root_partition.map.hdbx
..........\..............\...................\top_module.root_partition.map.kpt
..........\..............\README
..........\led0_module.v
..........\led1_module.v
..........\led2_module.v
..........\led3_module.v
..........\top_module.asm.rpt
..........\top_module.done
..........\top_module.fit.rpt
..........\top_module.fit.smsg
..........\top_module.fit.summary
..........\top_module.flow.rpt
..........\top_module.map.rpt
..........\top_module.map.summary
..........\top_module.pin
..........\top_module.pof
..........\top_module.qpf
..........\top_module.qsf
..........\top_module.qws
..........\top_module.sim.rpt
..........\top_module.sof
..........\top_module.tan.rpt
..........\top_module.tan.summary
..........\top_module.v
..........\top_module.v.bak
..........\top_module.vwf
..........\incremental_db\compiled_partitions
..........\db
..........\incremental_db
top_module