文件名称:FIR_dida

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [Matlab] [源码]
  • 上传时间:
  • 2013-08-26
  • 文件大小:
  • 1.43mb
  • 下载次数:
  • 5次
  • 提 供 者:
  • chen****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

自己写的FIR滤波器设计,verilog语言写的,很好用-Write your own FIR filter design, verilog language, easy to use
(系统自动生成,下载前可以参看下载内容)

下载文件列表





FIR_dida

........\FIR.asm.rpt

........\FIR.bsf

........\FIR.done

........\FIR.fit.rpt

........\FIR.fit.summary

........\FIR.flow.rpt

........\FIR.map.rpt

........\FIR.map.smsg

........\FIR.map.summary

........\FIR.pin

........\FIR.pof

........\FIR.qpf

........\FIR.qsf

........\FIR.qws

........\FIR.sim.rpt

........\FIR.sof

........\FIR.tan.rpt

........\FIR.tan.summary

........\FIR.v

........\FIR.v.bak

........\FIR.vwf

........\FIRFIR.bdf

........\FIR_1.bsf

........\FIR_1.html

........\FIR_1.qip

........\FIR_1.v

........\FIR_1.vec

........\FIR_1.vo

........\FIR_1_ast.vhd

........\FIR_1_bb.v

........\FIR_1_coef_int.txt

........\FIR_1_constraints.tcl

........\FIR_1_input.txt

........\FIR_1_mlab.m

........\FIR_1_model.m

........\FIR_1_msim.tcl

........\FIR_1_nativelink.tcl

........\FIR_1_param.txt

........\FIR_1_silent_param.txt

........\FIR_1_st.v

........\FIR_assignment_defaults.qdf

........\Hlp_tb.v

........\db

........\..\FIR.db_info

........\..\FIR.sim.cvwf

........\..\FIR.sld_design_entry.sci

........\..\prev_cmp_FIR.map.qmsg

........\..\prev_cmp_FIR.qmsg

........\..\prev_cmp_FIR.sim.qmsg

........\..\wed.wsf

........\fir_compiler-library

........\....................\accum.v

........\....................\addr_cnt_dn.v

........\....................\addr_cnt_dn_poly.v

........\....................\addr_cnt_up.v

........\....................\at_sink_mod.v

........\....................\at_sink_mod_bin.v

........\....................\at_sink_mod_par.v

........\....................\at_src_mod.v

........\....................\at_src_mod_par.v

........\....................\auk_dspip_avalon_streaming_block_sink_fir_90.vhd

........\....................\auk_dspip_avalon_streaming_block_source_fir_90.vhd

........\....................\auk_dspip_avalon_streaming_controller_fir_90.vhd

........\....................\auk_dspip_avalon_streaming_controller_pe_fir_90.vhd

........\....................\auk_dspip_avalon_streaming_monitor_fir_90.vhd

........\....................\auk_dspip_avalon_streaming_sink_fir_90.ocp

........\....................\auk_dspip_avalon_streaming_sink_fir_90.vhd

........\....................\auk_dspip_avalon_streaming_sink_model_fir_90.vhd

........\....................\auk_dspip_avalon_streaming_source_fir_90.vhd

........\....................\auk_dspip_avalon_streaming_source_from_monitor_fir_90.vhd

........\....................\auk_dspip_avalon_streaming_source_model_fir_90.vhd

........\....................\auk_dspip_delay_fir_90.vhd

........\....................\auk_dspip_fast_accumulator_fir_90.vhd

........\....................\auk_dspip_fastadd_fir_90.vhd

........\....................\auk_dspip_fastaddsub_fir_90.vhd

........\....................\auk_dspip_fifo_pfc_fir_90.vhd

........\....................\auk_dspip_fir_accumulator_fir_90.vhd

........\....................\auk_dspip_fir_adder_tree_fir_90.vhd

........\....................\auk_dspip_fir_adders_fir_90.vhd

........\....................\auk_dspip_fir_avalon_slave_write_fir_90.vhd

........\....................\auk_dspip_fir_coef_banks_fixed_fir_90.vhd

........\....................\auk_dspip_fir_data_memory_bank_fir_90.vhd

........\....................\auk_dspip_fir_dspblock_bank_fir_90.vhd

........\....................\auk_dspip_fir_dspblock_cascade_bank_fir_90.vhd

........\....................\auk_dspip_fir_lib_pkg_fir_90.vhd

........\....................\auk_dspip_fir_math_pkg_fir_90.vhd

........\....................\auk_dspip_fir_memory_simple_dual_fir_90.vhd

........\....................\auk_dspip_fir_memory_single_fir_90.vhd

........\....................\auk_dspip_fir_memory_true_dual_fir_90.vhd

........\....................\auk_dspip_fir_mult_bank_fir_90.vhd

........\....................\auk_dspip_fir_top_dec_half_sym_fir_90.ocp

........\....................\auk_dspip_fir_top_dec_half_sym_fir_90.vhd

........\....................\auk_dspip_fir_top_dec_sym_add_cas_fir_90.vhd

........\....................\auk_dspip_fir_top_dec_sym_cas_fir_90.ocp

........\....................\auk_dspip_fir_top_int_sym_fir_90.ocp

........\....................\auk_d

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