文件名称:fsm_seq_det
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog 状态机实现序列检测。简单明了，打开modelsim-change directory -do sim.do 即可-State machine sequence detection.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
work\sim\modelsim.ini
....\...\sim.do
....\...\sim.do.bak
....\...\vsim.wlf
....\...\wave.do
....\...\wave.do.wlf
....\...\.ork\div_clk\verilog.asm
....\...\....\.......\verilog.rw
....\...\....\.......\_primary.dat
....\...\....\.......\_primary.dbs
....\...\....\.......\_primary.vhd
....\...\....\sequence_det\verilog.asm
....\...\....\............\verilog.rw
....\...\....\............\_primary.dat
....\...\....\............\_primary.dbs
....\...\....\............\_primary.vhd
....\...\....\tb_div_clk\verilog.asm
....\...\....\..........\verilog.rw
....\...\....\..........\_primary.dat
....\...\....\..........\_primary.dbs
....\...\....\..........\_primary.vhd
....\...\....\...sequence_det\verilog.asm
....\...\....\...............\verilog.rw
....\...\....\...............\_primary.dat
....\...\....\...............\_primary.dbs
....\...\....\...............\_primary.vhd
....\...\....\_info
....\...\....\.temp\vlog01ywqq
....\...\....\.....\vlog02r1rb
....\...\....\.....\vlog1s1c8d
....\...\....\.....\vlog2q5gtd
....\...\....\.....\vlog2qf01e
....\...\....\.....\vlog34h7wx
....\...\....\.....\vlog3vt1gq
....\...\....\.....\vlog5zna2g
....\...\....\.....\vlog7hzvm4
....\...\....\.....\vlogb16mmk
....\...\....\.....\vlogbajaxd
....\...\....\.....\vlogf6ctr0
....\...\....\.....\vlogi1i97x
....\...\....\.....\vlogjic357
....\...\....\.....\vlogk8ydvd
....\...\....\.....\vlogkhxk6v
....\...\....\.....\vlogmvs3z7
....\...\....\.....\vlognyg4x4
....\...\....\.....\vlogr362xv
....\...\....\.....\vlogrj3sxa
....\...\....\.....\vlogrzc3x9
....\...\....\.....\vlogsq4ez4
....\...\....\.....\vlogwwnhtg
....\...\....\.....\vlogyib26n
....\...\....\_vmake
....\.rc\div.V.bak
....\...\div_clk.V
....\...\sequence_det.v
....\...\sequence_det.v.bak
....\tb\tb_div.v.bak
....\..\tb_div_clk.v.bak
....\..\tb_sequence_det.v
....\..\tb_sequence_det.v.bak
....\sim\work\div_clk
....\...\....\sequence_det
....\...\....\tb_div_clk
....\...\....\tb_sequence_det
....\...\....\_temp
....\...\work
....\sim
....\src
....\tb
work