文件名称:clockend
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基于QuartusII开发环境，Cyclone III开发板的VerilogHDL多功能数字钟程序。可实现24小时计时，手动校时，闹钟，整点报时功能。分频模块在仿真和烧写是需要改变。-QuartusII based development environment, Cyclone III development board VerilogHDL multifunction digital clock procedures. Can achieve 24-hour clock, manual timing, alarm, hourly chime functions. Frequency module in the simulation and programming needs to change.
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下载文件列表
clockend\clock.asm.rpt
........\clock.done
........\clock.dpf
........\clock.fit.rpt
........\clock.fit.smsg
........\clock.fit.summary
........\clock.flow.rpt
........\clock.map.rpt
........\clock.map.smsg
........\clock.map.summary
........\clock.pin
........\clock.qpf
........\clock.qsf
........\clock.qws
........\clock.sim.rpt
........\clock.sof
........\clock.sta.rpt
........\clock.sta.summary
........\clock.v
........\clock.v.bak
........\clock.vwf
........\db\clock.asm.qmsg
........\..\clock.asm.rdb
........\..\clock.cbx.xml
........\..\clock.cmp.cbp
........\..\clock.cmp.ecobp
........\..\clock.cmp.kpt
........\..\clock.cmp.rdb
........\..\clock.cmp_merge.kpt
........\..\clock.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
........\..\clock.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
........\..\clock.db_info
........\..\clock.eco.cdb
........\..\clock.eds_overflow
........\..\clock.fit.qmsg
........\..\clock.fnsim.cdb
........\..\clock.fnsim.hdb
........\..\clock.fnsim.qmsg
........\..\clock.hier_info
........\..\clock.hif
........\..\clock.lpc.html
........\..\clock.lpc.rdb
........\..\clock.lpc.txt
........\..\clock.map.bpm
........\..\clock.map.cdb
........\..\clock.map.ecobp
........\..\clock.map.hdb
........\..\clock.map.kpt
........\..\clock.map.logdb
........\..\clock.map.qmsg
........\..\clock.map_bb.cdb
........\..\clock.map_bb.hdb
........\..\clock.map_bb.logdb
........\..\clock.pre_map.cdb
........\..\clock.pre_map.hdb
........\..\clock.rtlv.hdb
........\..\clock.rtlv_sg.cdb
........\..\clock.rtlv_sg_swap.cdb
........\..\clock.sgdiff.cdb
........\..\clock.sgdiff.hdb
........\..\clock.sim.cvwf
........\..\clock.sim.hdb
........\..\clock.sim.qmsg
........\..\clock.sim.rdb
........\..\clock.simfam
........\..\clock.sld_design_entry.sci
........\..\clock.sld_design_entry_dsc.sci
........\..\clock.smart_action.txt
........\..\clock.sta.qmsg
........\..\clock.sta.rdb
........\..\clock.syn_hier_info
........\..\clock.tiscmp.fast_1200mv_0c.ddb
........\..\clock.tiscmp.slow_1200mv_0c.ddb
........\..\clock.tiscmp.slow_1200mv_85c.ddb
........\..\clock.tis_db_list.ddb
........\..\logic_util_heursitic.dat
........\..\prev_cmp_clock.asm.qmsg
........\..\prev_cmp_clock.fit.qmsg
........\..\prev_cmp_clock.map.qmsg
........\..\prev_cmp_clock.qmsg
........\..\prev_cmp_clock.sim.qmsg
........\..\prev_cmp_clock.sta.qmsg
........\..\wed.wsf
........\incremental_db\compiled_partitions\clock.root_partition.cmp.cdb
........\..............\...................\clock.root_partition.cmp.dfp
........\..............\...................\clock.root_partition.cmp.hdb
........\..............\...................\clock.root_partition.cmp.kpt
........\..............\...................\clock.root_partition.cmp.logdb
........\..............\...................\clock.root_partition.cmp.rcfdb
........\..............\...................\clock.root_partition.cmp.re.rcfdb
........\..............\...................\clock.root_partition.map.cdb
........\..............\...................\clock.root_partition.map.dpi
........\..............\...................\clock.root_partition.map.hdb
........\..............\...................\clock.root_partition.map.kpt
........\..............\README
........\..............\compiled_partitions
........\db
........\incremental_db
clockend