文件名称:SiDianDingWei
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用FPGA控制、Verilog HDL语言编写、实现在已知四点的情况下测量任意一点的功能-Using FPGA control, Verilog HDL language and realized in the case of the known four-point measurement function at any point
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下载文件列表
SiDianDingWei
.............\CH_CNT_EN.bsf
.............\CH_CNT_EN.v
.............\CH_CNT_EN.v.bak
.............\CNT.bsf
.............\CNT.v
.............\CNT.v.bak
.............\CNT_CLR.bsf
.............\CNT_CLR.v
.............\db
.............\..\phase.asm.qmsg
.............\..\phase.asm_labs.ddb
.............\..\phase.cbx.xml
.............\..\phase.cmp.bpm
.............\..\phase.cmp.cdb
.............\..\phase.cmp.ecobp
.............\..\phase.cmp.hdb
.............\..\phase.cmp.kpt
.............\..\phase.cmp.logdb
.............\..\phase.cmp.rdb
.............\..\phase.cmp.tdb
.............\..\phase.cmp0.ddb
.............\..\phase.cmp_merge.kpt
.............\..\phase.db_info
.............\..\phase.eco.cdb
.............\..\phase.eds_overflow
.............\..\phase.fit.qmsg
.............\..\phase.hier_info
.............\..\phase.hif
.............\..\phase.lpc.html
.............\..\phase.lpc.rdb
.............\..\phase.lpc.txt
.............\..\phase.map.bpm
.............\..\phase.map.cdb
.............\..\phase.map.ecobp
.............\..\phase.map.hdb
.............\..\phase.map.kpt
.............\..\phase.map.logdb
.............\..\phase.map.qmsg
.............\..\phase.map_bb.cdb
.............\..\phase.map_bb.hdb
.............\..\phase.map_bb.logdb
.............\..\phase.pre_map.cdb
.............\..\phase.pre_map.hdb
.............\..\phase.rtlv.hdb
.............\..\phase.rtlv_sg.cdb
.............\..\phase.rtlv_sg_swap.cdb
.............\..\phase.sgdiff.cdb
.............\..\phase.sgdiff.hdb
.............\..\phase.sim.cvwf
.............\..\phase.sim.hdb
.............\..\phase.sim.qmsg
.............\..\phase.sim.rdb
.............\..\phase.sld_design_entry.sci
.............\..\phase.sld_design_entry_dsc.sci
.............\..\phase.syn_hier_info
.............\..\phase.tan.qmsg
.............\..\phase.tis_db_list.ddb
.............\..\phase_global_asgn_op.abo
.............\..\prev_cmp_phase.asm.qmsg
.............\..\prev_cmp_phase.fit.qmsg
.............\..\prev_cmp_phase.map.qmsg
.............\..\prev_cmp_phase.qmsg
.............\..\prev_cmp_phase.sim.qmsg
.............\..\prev_cmp_phase.tan.qmsg
.............\..\wed.wsf
.............\fpga.wsp
.............\incremental_db
.............\..............\compiled_partitions
.............\..............\...................\phase.root_partition.cmp.atm
.............\..............\...................\phase.root_partition.cmp.dfp
.............\..............\...................\phase.root_partition.cmp.hdbx
.............\..............\...................\phase.root_partition.cmp.kpt
.............\..............\...................\phase.root_partition.cmp.logdb
.............\..............\...................\phase.root_partition.cmp.rcf
.............\..............\...................\phase.root_partition.map.atm
.............\..............\...................\phase.root_partition.map.dpi
.............\..............\...................\phase.root_partition.map.hdbx
.............\..............\...................\phase.root_partition.map.kpt
.............\..............\README
.............\MUX_80.bsf
.............\MUX_80.v
.............\MUX_80.v.bak
.............\phase.asm.rpt
.............\phase.bdf
.............\phase.done
.............\phase.dpf
.............\phase.fit.rpt
.............\phase.fit.smsg
.............\phase.fit.summary
.............\phase.flow.rpt
.............\phase.map.rpt
.............\phase.map.summary
.............\phase.pin
.............\phase.pof
.............\phase.qpf
.............\phase.qsf
.............\phase.qws
.............\phase.sim.rpt
.............\phase.sof