文件名称:I2C_slavemodule

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2013-07-16
  • 文件大小:
  • 1.85mb
  • 下载次数:
  • 0次
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  • 别用迅雷下载,失败请重下,重下不扣分!

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Verilog I2C 转SPI 总线代码,在MAX EP240上成功使用,设计很简洁,很不错-Verilog I2C TO spi code
(系统自动生成,下载前可以参看下载内容)

下载文件列表





I2C_slavemodule\clk_div.v

...............\clk_div.v.bak

...............\History\I2Cslave_Mod1.~(1).v.Zip

...............\.......\I2Cslave_Mod1.~(2).v.Zip

...............\.......\I2Cslave_Mod1.~(3).v.Zip

...............\.......\sim_main.~(1).v.Zip

...............\.......\sim_main.~(10).v.Zip

...............\.......\sim_main.~(11).v.Zip

...............\.......\sim_main.~(12).v.Zip

...............\.......\sim_main.~(13).v.Zip

...............\.......\sim_main.~(14).v.Zip

...............\.......\sim_main.~(15).v.Zip

...............\.......\sim_main.~(2).v.Zip

...............\.......\sim_main.~(3).v.Zip

...............\.......\sim_main.~(4).v.Zip

...............\.......\sim_main.~(5).v.Zip

...............\.......\sim_main.~(6).v.Zip

...............\.......\sim_main.~(7).v.Zip

...............\.......\sim_main.~(8).v.Zip

...............\.......\sim_main.~(9).v.Zip

...............\I2Cslave_Mod1.v

...............\I2Cslave_Mod1.v.bak

...............\I2Cslave_Mod1.vPreview

...............\I2Cslave_Top.v.bak

...............\I2C_slave_Top.v

...............\I2C_slave_Top.v.bak

...............\I2C_TO_SPI.v

...............\I2C_TO_SPI.v.bak

...............\modelsim.ini

...............\proj.prd

...............\proj.prj

...............\rev_1\.recordref

...............\.....\AutoConstraint_I2C_TO_SPI.sdc

...............\.....\backup\I2Cslave_Mod1.srr

...............\.....\I2Cslave_Mod1.areasrr

...............\.....\I2Cslave_Mod1.edn

...............\.....\I2Cslave_Mod1.fse

...............\.....\I2Cslave_Mod1.htm

...............\.....\I2Cslave_Mod1.map

...............\.....\I2Cslave_Mod1.sap

...............\.....\I2Cslave_Mod1.sdf

...............\.....\I2Cslave_Mod1.srd

...............\.....\I2Cslave_Mod1.srm

...............\.....\I2Cslave_Mod1.srr

...............\.....\I2Cslave_Mod1.srs

...............\.....\I2Cslave_Mod1.tlg

...............\.....\I2Cslave_Mod1_sdc.sdc

...............\.....\run_options.txt

...............\.....\syntmp\I2Cslave_Mod1.msg

...............\.....\......\I2Cslave_Mod1.plg

...............\.....\......\I2Cslave_Mod1_flink.htm

...............\.....\......\I2Cslave_Mod1_srr.htm

...............\.....\......\I2Cslave_Mod1_toc.htm

...............\.....\......\proj_flink.htm

...............\.....\......\sap.log

...............\.....\traplog.tlg

...............\....2\syntmp\I2Cslave_Mod1.msg

...............\sim_I2C-slave_1.png

...............\sim_main.v

...............\sim_main.v.bak

...............\sim_main.vPreview

...............\SPI_Master.v

...............\SPI_Master.v.bak

...............\spi_top.v

...............\SPI_TOP.v.bak

...............\transcript

...............\vish_stacktrace.vstf

...............\vlog.opt

...............\vsim.wlf

...............\work\@i2@cslave@with8bits@i@o\verilog.psm

...............\....\........................\_primary.dat

...............\....\........................\_primary.dbs

...............\....\........................\_primary.vhd

...............\....\....._@t@o_@s@p@i\verilog.psm

...............\....\.................\_primary.dat

...............\....\.................\_primary.dbs

...............\....\.................\_primary.vhd

...............\....\....s@l@a@v@e@r_@t@o@p\verilog.psm

...............\....\......................\_primary.dat

...............\....\......................\_primary.dbs

...............\....\......................\_primary.vhd

...............\....\..@i@c_@s@l@a@v@e@r_@t@o@p\verilog.psm

...............\....\..........................\_primary.dat

...............\....\..........................\_primary.dbs

...............\....\..........................\_primary.vhd

...............\....\.s@p@i_@master\verilog.psm

...............\....\..............\_primary.dat

...............\....\..............\_primary.dbs

...............\....\..............\_primary.vhd

...............\....\clk_div\verilog.psm

...............\....\.......\_primary.dat

...............\....\.......\_primary.dbs

...............\....\.......\_primary.vhd

...............\....\sim_main\verilog.psm

...............\....\........\_primary.dat

...............\....\........\_primary.dbs

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