文件名称:full_add4_ok_
介绍说明－－下载内容均来自于网络，请自行研究使用
Learning FPGA students can see, this code USES VHDL language to write four full adder, not only can learn QUARTUS software, also can better enhance the digital circuit design.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
full_add4_ok_4位全加器\db\full_add4.asm.qmsg
......................\..\full_add4.asm_labs.ddb
......................\..\full_add4.cbx.xml
......................\..\full_add4.cmp.cdb
......................\..\full_add4.cmp.hdb
......................\..\full_add4.cmp.kpt
......................\..\full_add4.cmp.logdb
......................\..\full_add4.cmp.rdb
......................\..\full_add4.cmp.tdb
......................\..\full_add4.cmp0.ddb
......................\..\full_add4.dbp
......................\..\full_add4.db_info
......................\..\full_add4.eco.cdb
......................\..\full_add4.eds_overflow
......................\..\full_add4.fit.qmsg
......................\..\full_add4.hier_info
......................\..\full_add4.hif
......................\..\full_add4.map.cdb
......................\..\full_add4.map.hdb
......................\..\full_add4.map.logdb
......................\..\full_add4.map.qmsg
......................\..\full_add4.pre_map.cdb
......................\..\full_add4.pre_map.hdb
......................\..\full_add4.psp
......................\..\full_add4.rtlv.hdb
......................\..\full_add4.rtlv_sg.cdb
......................\..\full_add4.rtlv_sg_swap.cdb
......................\..\full_add4.sgdiff.cdb
......................\..\full_add4.sgdiff.hdb
......................\..\full_add4.signalprobe.cdb
......................\..\full_add4.sim.hdb
......................\..\full_add4.sim.qmsg
......................\..\full_add4.sim.rdb
......................\..\full_add4.sim_ori.vwf
......................\..\full_add4.sld_design_entry.sci
......................\..\full_add4.sld_design_entry_dsc.sci
......................\..\full_add4.syn_hier_info
......................\..\full_add4.tan.qmsg
......................\..\wed.zsf
......................\full_add4.asm.rpt
......................\full_add4.done
......................\full_add4.fit.rpt
......................\full_add4.fit.smsg
......................\full_add4.fit.summary
......................\full_add4.flow.rpt
......................\full_add4.map.rpt
......................\full_add4.map.summary
......................\full_add4.pin
......................\full_add4.pof
......................\full_add4.qpf
......................\full_add4.qsf
......................\full_add4.qws
......................\full_add4.sim.rpt
......................\full_add4.tan.rpt
......................\full_add4.tan.summary
......................\full_add4.vhd
......................\full_add4.vwf
......................\full_add4程序逐行解释.doc
......................\db
full_add4_ok_4位全加器