文件名称:timer_VHDL
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实现对秒信号分频到ms级，通过异步串口接收时分秒信号，将这些信号连同ms信号并送给同步串口-Achieve the second signal is divided into ms level, through an asynchronous serial receiver, hour signal, signals and these signals are sent along with ms synchronous serial
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下载文件列表
timer_VHDL\.lso
..........\Analysis 1.twx
..........\asyn_uart\uart.v
..........\.........\uart_transceiver.v
..........\.........\vsim.wlf
..........\.........\wave_auart.do
..........\clock_topology.twr
..........\iseconfig\sys_top_module.xreport
..........\.........\timer_count.xreport
..........\.........\timer_design.projectmgr
..........\.........\uart.xreport
..........\mr_ad.vhd.bak
..........\pa.fromNcd.tcl
..........\planAhead.ngc2edif.log
..........\rz_DivArrUns.vhd
..........\signal_syn.cmd_log
..........\signal_syn.lso
..........\signal_syn.ngc
..........\signal_syn.ngr
..........\signal_syn.prj
..........\signal_syn.stx
..........\signal_syn.syr
..........\signal_syn.vhd
..........\signal_syn.xst
..........\signal_syn_envsettings.html
..........\signal_syn_summary.html
..........\signal_syn_vhdl.prj
..........\signal_syn_xst.xrpt
..........\.yn_uart\syn_uart.vhd
..........\........\vish_stacktrace.vstf
..........\........\vsim.wlf
..........\........\wave.do
..........\syn_uart.cmd_log
..........\syn_uart.lso
..........\syn_uart.ngc
..........\syn_uart.ngr
..........\syn_uart.prj
..........\syn_uart.stx
..........\syn_uart.syr
..........\syn_uart.xst
..........\syn_uart_envsettings.html
..........\syn_uart_summary.html
..........\syn_uart_vhdl.prj
..........\syn_uart_xst.xrpt
..........\system.ucf
..........\system.ucf.bak
..........\sys_top_module.bgn
..........\sys_top_module.bit
..........\sys_top_module.bld
..........\sys_top_module.cmd_log
..........\sys_top_module.drc
..........\sys_top_module.lso
..........\sys_top_module.pad
..........\sys_top_module.par
..........\sys_top_module.pcf
..........\sys_top_module.prj
..........\sys_top_module.ptwx
..........\sys_top_module.stx
..........\sys_top_module.syr
..........\sys_top_module.twr
..........\sys_top_module.twx
..........\sys_top_module.unroutes
..........\sys_top_module.ut
..........\sys_top_module.vhd
..........\sys_top_module.vhd.bak
..........\sys_top_module.xpi
..........\sys_top_module.xst
..........\sys_top_module_bitgen.xwbt
..........\sys_top_module_envsettings.html
..........\sys_top_module_fpga_editor.log
..........\sys_top_module_map.map
..........\sys_top_module_map.mrp
..........\sys_top_module_map.ncd
..........\sys_top_module_map.xrpt
..........\sys_top_module_ngdbuild.xrpt
..........\sys_top_module_pad.csv
..........\sys_top_module_summary.html
..........\sys_top_module_summary.xml
..........\sys_top_module_usage.xml
..........\sys_top_module_vhdl.prj
..........\sys_top_module_xst.xrpt
..........\timer_count.cmd_log
..........\timer_count.lso
..........\timer_count.prj
..........\timer_count.stx
..........\timer_count.syr
..........\timer_count.vhd
..........\timer_count.xst
..........\timer_count_envsettings.html
..........\timer_count_summary.html
..........\timer_count_vhdl.prj
..........\timer_count_xst.xrpt
..........\timer_design.gise
..........\timer_design.xise
..........\uart.cmd_log
..........\uart.lso
..........\uart.ngc
..........\uart.prj
..........\uart.stx
..........\uart.syr