文件名称:uart16550_VERLOG
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介绍说明－－下载内容均来自于网络，请自行研究使用
采用VERILOG实现完整的UART16550协议，提供RTL代码、仿真文件-Using VERILOG achieve a complete UART16550 agreement to provide RTL code, simulation files
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下载文件列表
uart16550_VERLOG\bench\verilog\readme.txt
................\.....\.......\test_cases\uart_int.v
................\.....\.......\uart_device.v
................\.....\.......\uart_device_utilities.v
................\.....\.......\uart_log.v
................\.....\.......\uart_test.v
................\.....\.......\uart_testbench.v
................\.....\.......\uart_testbench_defines.v
................\.....\.......\uart_testbench_utilities.v
................\.....\.......\uart_wb_utilities.v
................\.....\.......\vapi.log
................\.....\.......\wb_mast.v
................\.....\.......\wb_master_model.v
................\.....\.......\wb_model_defines.v
................\rtl\verilog\raminfr.v
................\...\.......\timescale.v
................\...\.......\uart_debug_if.v
................\...\.......\uart_defines.v
................\...\.......\uart_receiver.v
................\...\.......\uart_regs.v
................\...\.......\uart_rfifo.v
................\...\.......\uart_sync_flops.v
................\...\.......\uart_tfifo.v
................\...\.......\uart_top.v
................\...\.......\uart_transmitter.v
................\...\.......\uart_wb.v
................\sim\gate_sim\bin\.keepme
................\...\........\log\.keepme
................\...\........\out\.keepme
................\...\........\run\.keepme
................\...\........\src\.keepme
................\...\rtl_sim\bin\nc.scr
................\...\.......\...\sim.tcl
................\...\.......\log\.keepme
................\...\.......\...\uart_interrupts_report.log
................\...\.......\...\uart_interrupts_verbose.log
................\...\.......\out\.keepme
................\...\.......\run\run_signalscan
................\...\.......\...\run_sim
................\...\.......\...\run_sim.scr
................\...\.......\src\.keepme
................\bench\verilog\test_cases
................\sim\gate_sim\bin
................\...\........\log
................\...\........\out
................\...\........\run
................\...\........\src
................\...\rtl_sim\bin
................\...\.......\log
................\...\.......\out
................\...\.......\run
................\...\.......\src
................\bench\verilog
................\rtl\verilog
................\sim\gate_sim
................\...\rtl_sim
................\bench
................\rtl
................\sim
uart16550_VERLOG