文件名称:cpu_if
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设计上的约束：
1 地址线和数据线公用
2 一个压力数据有12位，使用两次传输
3 总共有14根信号，8根用于地址和数据，剩余六根做控制。
cs_n: 片选信号，为低表示传输开始
rd_nwr:读写标示信号，1表示读；0表示写。
Ale：address latch enable，为1时，表示当前ad线上的是地址信号，为0时，表示当前ad线上的是数据信号。
A_D(共八根)：地址和数据公用线，共八根
-Design constraints: an address and data lines, a public two pressure data with 12, with a total of two transmission 3 14 Signal, 8 for address and data, and the remaining six as a control. cs_n: chip select signal is low indicates that the transmission start rd_nwr: literacy labeled signal 1 is read 0 indicates a write. Ale: address latch enable, is 1, which means that the current ad line address signal is 0, it indicates that the data signal line ad. A_D (a total of eight): Public address and data lines, a total of eight
1 地址线和数据线公用
2 一个压力数据有12位，使用两次传输
3 总共有14根信号，8根用于地址和数据，剩余六根做控制。
cs_n: 片选信号，为低表示传输开始
rd_nwr:读写标示信号，1表示读；0表示写。
Ale：address latch enable，为1时，表示当前ad线上的是地址信号，为0时，表示当前ad线上的是数据信号。
A_D(共八根)：地址和数据公用线，共八根
-Design constraints: an address and data lines, a public two pressure data with 12, with a total of two transmission 3 14 Signal, 8 for address and data, and the remaining six as a control. cs_n: chip select signal is low indicates that the transmission start rd_nwr: literacy labeled signal 1 is read 0 indicates a write. Ale: address latch enable, is 1, which means that the current ad line address signal is 0, it indicates that the data signal line ad. A_D (a total of eight): Public address and data lines, a total of eight
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cpu_if.v