文件名称:Verilog

  • 所属分类:
  • 书籍源码
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2013-06-23
  • 文件大小:
  • 128kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • huar*****
  • 相关连接:
  • 下载说明:
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无线通信FPGA设计_代码 无线通信FPGA设计_代码-FPGA design _ code wireless communications wireless communications wireless communications FPGA design _ code _ code for FPGA design
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Verilog代码\c10\10-2\mult.xco

...........\...\....\mydds.xco

...........\...\....\square_syn.v

...........\...\...4\coastas_dds.v

...........\...\....\costas_lf.v

...........\...\....\costas_loop.v

...........\...\....\costas_lpf.v

...........\...\....\costas_mult.v

...........\...\....\err_mult.v

...........\...\....\fir_lpf.xco

...........\...\....\mult.xco

...........\...\....\my_dds.xco

...........\...\...6\dearly_sub.v

...........\...\....\dedds.v

...........\...\....\delay_early_gate.v

...........\...\....\de_mult.xco

...........\...\....\eddds.xco

...........\...\....\iir.v

...........\...\....\iir1.v

...........\...\...8\baker.v

...........\..1\11-10\div16.xco

...........\...\.....\fir_rls.v

...........\...\.....\rlsmult.xco

...........\...\.....\shiftreg25.xco

...........\...\.....\shiftreg28.xco

...........\...\.....\shiftreg3.xco

...........\...\....2\dfe_filter.v

...........\...\.....\dfe_mult.xco

...........\...\....4\aa_adder.xco

...........\...\.....\aa_bram.xco

...........\...\.....\aa_cmult.xco

...........\...\.....\ad_a.v

...........\...\.....\shift16.xco

...........\...\...2\fir_lms.v

...........\...\...3\fir_pipline_lms.v

...........\...\....\lmsmult.xco

...........\...\...5\mult.xco

...........\...\....\shiftreg4.xco

...........\...\....\sign_fir_lms.v

...........\...\...8\blockconnect.v

...........\...\....\cmult.v

...........\...\....\coe_updata.v

...........\...\....\complex_mult.xco

...........\...\....\fft_block.v

...........\...\....\fft_block_lms.v

...........\...\....\fft_w16_p32.xco

...........\...\....\gonge.v

...........\...\....\ifft_block.v

...........\...\....\insert.v

...........\...\....\save_sub.v

...........\...\....\shiftreg.xco

...........\...\....\shiftreg3.xco

...........\...\....\shift_reg2.xco

...........\...\....\srl16_w16_d16.xco

...........\...\....\test_block_connect.v

...........\..2_0\12-6\rake_cmult.xco

...........\.....\....\rake_mrc.v

...........\.....\....\rake_shift4.xco

...........\..3\13-2\ovsf.v

...........\...\...3\Dscamb.v

...........\...\...6\adder_18vs18.xco

...........\...\....\CPICH.v

...........\...\....\ram_1024.xco

...........\...\....\ram_descramb.xco

...........\.3\3-22\adder8.v

...........\..\...3\adder8_2.v

...........\..\...4\adder8_4.v

...........\.5\5-1\adder16_2.v

...........\..\...0\div16.xco

...........\..\....\div16_1.v

...........\..\...1\divf16.xco

...........\..\....\divf16_1.v

...........\..\...5\dds.v

...........\..\....\rom_cos.coe

...........\..\....\rom_cose.xco

...........\..\....\rom_sin.coe

...........\..\....\rom_sine.xco

...........\..\...6\dds1.v

...........\..\....\mydds.xco

...........\..\...7\cordic.v

...........\..\...8\sqrt.xco

...........\..\....\sqrt1.v

...........\..\..2\add_4.v

...........\..\..3\adder.xco

...........\..\...\adder1.v

...........\..\..4\ade.v

...........\..\..5\mul_addtree.v

...........\..\..6\cmultip.v

...........\..\...\rmulti.xco

...........\..\..7\mult_8.v

...........\..\..9\divider.v

...........\.6\6-15\IIR_Filter_8.v

...........\..\...7\iir_c.v

...........\..\....\sub2.v

...........\..\...8\iir_pipeline.v

...........\..\..20\iir_par.v

...........\..\...3\rrc_128.coe

...........\..\..4\FIR_lowpass.v

...........\..\..5\mult.xco

...........\..\...\ser_fir.v

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