文件名称:Examples

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  • 编辑器/阅读器
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  • 上传时间:
  • 2013-06-12
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  • 13.66mb
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  • fu***
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source code of altium designer 10
(系统自动生成,下载前可以参看下载内容)

下载文件列表





DB31 Altera Cyclone II F672\Bypass_FPGA_1V2.SCHDOC

...........................\Bypass_FPGA_3V3.SchDoc

...........................\DB31.Annotation

...........................\DB31.Dat

...........................\DB31.PcbDoc

...........................\DB31.PRJPCB

...........................\DB31.PRJPCBStructure

...........................\DB31_Hardware_Kit.SchDoc

...........................\DB31_Panel.OutJob

...........................\DB31_Panel.PcbDoc

...........................\DB31_Top.SchDoc

...........................\.ependencies\Device Sheets\1WB_DS2406_EPROM.Harness

...........................\............\.............\1WB_DS2406_EPROM.SchDoc

...........................\............\.............\DB_Bypass.SchDoc

...........................\............\.............\DB_Common.SchDoc

...........................\............\.............\DB_LEDS.SchDoc

...........................\............\.............\DB_MotherBoardConnectors.Harness

...........................\............\.............\DB_MotherBoardConnectors.SchDoc

...........................\............\.............\DB_MOUNTS.SchDoc

...........................\............\.............\FLASH_S29GL256N11FFIV10_16Mx16.Harness

...........................\............\.............\FLASH_S29GL256N11FFIV10_16Mx16.SchDoc

...........................\............\.............\NB2_CommonMemory.Harness

...........................\............\.............\NB2_CommonMemory.SchDoc

...........................\............\.............\NB2_CommonMemory_Termination.Harness

...........................\............\.............\NB2_CommonMemory_Termination.SchDoc

...........................\............\.............\PSU_MAX1831_1V2_ALT.SchDoc

...........................\............\.............\SDRAM_MT48LC16M16A2TG_16Mx32.Harness

...........................\............\.............\SDRAM_MT48LC16M16A2TG_16Mx32.SchDoc

...........................\............\.............\SRAM_256Kx16_TSOP44.Harness

...........................\............\.............\SRAM_256Kx16_TSOP44.SchDoc

...........................\............\.............\SRAM_256Kx32_TSOP44_1.Harness

...........................\............\.............\SRAM_256Kx32_TSOP44_1.SchDoc

...........................\DEVICES.SchDoc

...........................\FPGA.Harness

...........................\FPGA.SCHDOC

...........................\FPGA_NonIO.SchDoc

...........................\PSU.SCHDOC

..46 Xilinx Virtex4-XC4VSX35\Bypass_FPGA_1V2.SCHDOC

............................\Bypass_FPGA_2V5.SCHDOC

............................\Bypass_FPGA_3V3.SchDoc

............................\DB46.Annotation

............................\DB46.PcbDoc

............................\DB46.PRJPCB

............................\DB46.PRJPCBStructure

............................\DB46_Hardware_Kit.SchDoc

............................\DB46_Panel.OutJob

............................\DB46_Panel.PcbDoc

............................\DB46_Top.SchDoc

............................\.ependencies\Device Sheets\1WB_DS2406_EPROM.Harness

............................\............\.............\1WB_DS2406_EPROM.SchDoc

............................\............\.............\DB_Bypass.SchDoc

............................\............\.............\DB_Common.SchDoc

............................\............\.............\DB_LEDS.SchDoc

............................\............\.............\DB_MotherBoardConnectors.Harness

............................\............\.............\DB_MotherBoardConnectors.SchDoc

............................\............\.............\DB_MOUNTS.SchDoc

............................\............\.............\FLASH_S29GL256N11FFIV10_16Mx16.Harness

............................\............\.............\FLASH_S29GL256N11FFIV10_16Mx16.SchDoc

............................\............\.............\NB2_CommonMemory.Harness

............................\............\.............\NB2_CommonMemory.SchDoc

............................\............\.............\NB2_CommonMemory_Termination.Harness

............................\........

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