文件名称:canbus
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can总线的开发和设计，基于FPGA，很强大-can bus development and design, based on FPGA, very powerful
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下载文件列表
Chapter9 Sample
...............\canbus
...............\......\.untf
...............\......\__projnav
...............\......\.........\can_fifo.xst
...............\......\.........\can_register_asyn_syn.xst
...............\......\.........\can_registers.xst
...............\......\.........\can_top.xst
...............\......\.........\canbus.gfl
...............\......\.........\canbus_flowplus.gfl
...............\......\.........\coregen.rsp
...............\......\.........\ednTOngd_tcl.rsp
...............\......\.........\runXst_tcl.rsp
...............\......\.........\xst_sprjTOstx_tcl.rsp
...............\......\__projnav.log
...............\......\_ngo
...............\......\....\netlist.lst
...............\......\automake.log
...............\......\can_acf.v
...............\......\can_bsp.v
...............\......\can_btl.v
...............\......\can_crc.v
...............\......\can_defines.v
...............\......\can_fifo.cmd_log
...............\......\can_fifo.lso
...............\......\can_fifo.ngc
...............\......\can_fifo.ngr
...............\......\can_fifo.prj
...............\......\can_fifo.stx
...............\......\can_fifo.syr
...............\......\can_fifo.v
...............\......\can_fifo_vhdl.prj
...............\......\can_ibo.v
...............\......\can_register.v
...............\......\can_register_asyn.v
...............\......\can_register_asyn_syn.cmd_log
...............\......\can_register_asyn_syn.lso
...............\......\can_register_asyn_syn.ngc
...............\......\can_register_asyn_syn.ngr
...............\......\can_register_asyn_syn.prj
...............\......\can_register_asyn_syn.stx
...............\......\can_register_asyn_syn.syr
...............\......\can_register_asyn_syn.v
...............\......\can_register_asyn_syn_vhdl.prj
...............\......\can_register_syn.v
...............\......\can_registers.lso
...............\......\can_registers.prj
...............\......\can_registers.stx
...............\......\can_registers.v
...............\......\can_registers_vhdl.prj
...............\......\can_testbench.fdo
...............\......\can_testbench.ndo
...............\......\can_testbench.udo
...............\......\can_testbench.v
...............\......\can_testbench_defines.v
...............\......\can_top.bld
...............\......\can_top.cmd_log
...............\......\can_top.ldo
...............\......\can_top.lso
...............\......\can_top.ngc
...............\......\can_top.ngd
...............\......\can_top.ngr
...............\......\can_top.prj
...............\......\can_top.stx
...............\......\can_top.syr
...............\......\can_top.v
...............\......\can_top.vhdsim_xlate
...............\......\can_top.xlate_nlf
...............\......\can_top_translate.nlf
...............\......\can_top_translate.vhd
...............\......\can_top_vhdl.prj
...............\......\canbus.dhp
...............\......\canbus.npl
...............\......\coregen.log
...............\......\coregen.prj
...............\......\prjname.lso
...............\......\timescale.v
...............\......\transcript
...............\......\work
...............\......\....\_info
...............\......\....\can_acf
...............\......\....\.......\_primary.dat
...............\......\....\.......\_primary.vhd
...............\......\....\.......\verilog.asm
...............\......\....\can_bsp
...............\......\....\.......\_primary.dat
...............\......\....\.......\_primary.vhd
...............\......\....\.......\verilog.asm
...............\......\....\can_btl
...............\......\....\.......\_primary.dat
...............\......\....\.......\_primary.vhd
...............\......\....\.......\verilog.asm
...............\......\....\can_crc
...............\......\....\.......\_primary.dat
...............\......\....\.......\_primary.vhd
...............\......\....\.......\verilog.asm
...............\......\....\can_fifo
...............\......\....\........\_primary.dat
...............\......\....\........\_primary.vhd
...............\......\....\........\verilog.asm