文件名称:CPU
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东南大学VHDL课程CPU设计 Verilog语言-Southeast University, CPU design Verilog language VHDL course
(系统自动生成,下载前可以参看下载内容)
下载文件列表
BR.bsf
BR.v
CU.bsf
CU.v
IR.bsf
IR.v
MAR.bsf
MAR.v
MBR.bsf
MBR.v
PC.bsf
PC.v
prev_cmp_TEST_CPU.qmsg
RAM.bsf
RAM.mif
RAM.v
RAM_bb.v
RAM_wave0.jpg
RAM_wave1.jpg
RAM_waveforms.html
ROM.mif
TEST_CPU.asm.rpt
Test_CPU.bdf
Test_CPU.done
TEST_CPU.fit.rpt
Test_CPU.fit.smsg
Test_CPU.fit.summary
TEST_CPU.flow.rpt
TEST_CPU.map.rpt
Test_CPU.map.summary
Test_CPU.pin
Test_CPU.pof
TEST_CPU.qpf
Test_CPU.qsf
TEST_CPU.qws
TEST_CPU.sim.rpt
Test_CPU.sof
TEST_CPU.tan.rpt
Test_CPU.tan.summary
TEST_CPU.vwf
Test_CPU_assignment_defaults.qdf
undo_redo.txt
db\add_sub_3dc.tdf
..\add_sub_3ph.tdf
..\add_sub_4dc.tdf
..\add_sub_4ph.tdf
..\add_sub_5dc.tdf
..\add_sub_6dc.tdf
..\add_sub_6rh.tdf
..\add_sub_7dc.tdf
..\add_sub_7eh.tdf
..\add_sub_8dc.tdf
..\add_sub_8eh.tdf
..\add_sub_8rh.tdf
..\add_sub_9dc.tdf
..\add_sub_9eh.tdf
..\add_sub_9gh.tdf
..\add_sub_adc.tdf
..\add_sub_aeh.tdf
..\add_sub_bdc.tdf
..\add_sub_beh.tdf
..\add_sub_ceh.tdf
..\add_sub_deh.tdf
..\add_sub_jec.tdf
..\add_sub_kec.tdf
..\add_sub_lec.tdf
..\add_sub_mec.tdf
..\add_sub_nec.tdf
..\add_sub_oac.tdf
..\add_sub_oec.tdf
..\add_sub_pch.tdf
..\add_sub_pec.tdf
..\altsyncram_41c1.tdf
..\altsyncram_mnc1.tdf
..\altsyncram_n9v.tdf
..\altsyncram_nbv.tdf
..\altsyncram_o9c1.tdf
..\alt_u_div_aue.tdf
..\lpm_divide_5hm.tdf
..\lpm_divide_h8m.tdf
..\mult_b011.tdf
..\mult_nn01.tdf
..\mux_0hc.tdf
..\mux_1hc.tdf
..\mux_lpc.tdf
..\prev_cmp_TEST_CPU.asm.qmsg
..\prev_cmp_TEST_CPU.fit.qmsg
..\prev_cmp_TEST_CPU.map.qmsg
..\prev_cmp_Test_CPU.qmsg
..\prev_cmp_TEST_CPU.sim.qmsg
..\prev_cmp_TEST_CPU.tan.qmsg
..\sign_div_unsign_dnh.tdf
..\TEST_CPU.db_info
..\TEST_CPU.eco.cdb
..\TEST_CPU.sim.cvwf
..\TEST_CPU.sim_ori.vwf
..\TEST_CPU.sld_design_entry.sci
..\Test_CPU0.rtl.mif
..\Test_CPU_global_asgn_op.abo
..\wed.wsf