文件名称:project4_1
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D触发器门级实现，有异步复位置位，HDl verilog语言编写，能在DE2上运行-D flip-flop gate-level implementation, there are asynchronous Reset_Set, HDl verilog language, able to run on the DE2
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下载文件列表
project4_1
..........\db
..........\..\prev_cmp_project4_1.asm.qmsg
..........\..\prev_cmp_project4_1.fit.qmsg
..........\..\prev_cmp_project4_1.map.qmsg
..........\..\prev_cmp_project4_1.qmsg
..........\..\prev_cmp_project4_1.sim.qmsg
..........\..\prev_cmp_project4_1.tan.qmsg
..........\..\project4_1.asm.qmsg
..........\..\project4_1.asm_labs.ddb
..........\..\project4_1.cbx.xml
..........\..\project4_1.cmp.bpm
..........\..\project4_1.cmp.cdb
..........\..\project4_1.cmp.ecobp
..........\..\project4_1.cmp.hdb
..........\..\project4_1.cmp.logdb
..........\..\project4_1.cmp.rdb
..........\..\project4_1.cmp.tdb
..........\..\project4_1.cmp0.ddb
..........\..\project4_1.cmp_bb.cdb
..........\..\project4_1.cmp_bb.hdb
..........\..\project4_1.cmp_bb.logdb
..........\..\project4_1.cmp_bb.rcf
..........\..\project4_1.dbp
..........\..\project4_1.db_info
..........\..\project4_1.eco.cdb
..........\..\project4_1.eds_overflow
..........\..\project4_1.fit.qmsg
..........\..\project4_1.fnsim.cdb
..........\..\project4_1.fnsim.hdb
..........\..\project4_1.fnsim.qmsg
..........\..\project4_1.hier_info
..........\..\project4_1.hif
..........\..\project4_1.map.bpm
..........\..\project4_1.map.cdb
..........\..\project4_1.map.ecobp
..........\..\project4_1.map.hdb
..........\..\project4_1.map.logdb
..........\..\project4_1.map.qmsg
..........\..\project4_1.map_bb.cdb
..........\..\project4_1.map_bb.hdb
..........\..\project4_1.map_bb.logdb
..........\..\project4_1.pre_map.cdb
..........\..\project4_1.pre_map.hdb
..........\..\project4_1.psp
..........\..\project4_1.pss
..........\..\project4_1.rpp.qmsg
..........\..\project4_1.rtlv.hdb
..........\..\project4_1.rtlv_sg.cdb
..........\..\project4_1.rtlv_sg_swap.cdb
..........\..\project4_1.sgate.rvd
..........\..\project4_1.sgate_sm.rvd
..........\..\project4_1.sgdiff.cdb
..........\..\project4_1.sgdiff.hdb
..........\..\project4_1.signalprobe.cdb
..........\..\project4_1.sim.cvwf
..........\..\project4_1.sim.hdb
..........\..\project4_1.sim.qmsg
..........\..\project4_1.sim.rdb
..........\..\project4_1.simfam
..........\..\project4_1.sld_design_entry.sci
..........\..\project4_1.sld_design_entry_dsc.sci
..........\..\project4_1.syn_hier_info
..........\..\project4_1.tan.qmsg
..........\..\project4_1.tis_db_list.ddb
..........\..\wed.wsf
..........\project4_1.asm.rpt
..........\project4_1.done
..........\project4_1.dpf
..........\project4_1.fit.rpt
..........\project4_1.fit.summary
..........\project4_1.flow.rpt
..........\project4_1.map.rpt
..........\project4_1.map.smsg
..........\project4_1.map.summary
..........\project4_1.pin
..........\project4_1.pof
..........\project4_1.qpf
..........\project4_1.qsf
..........\project4_1.qws
..........\project4_1.sim.rpt
..........\project4_1.sof
..........\project4_1.tan.rpt
..........\project4_1.tan.summary
..........\project4_1.v
..........\project4_1.v.bak
..........\project4_1.vwf
..........\project4_1_description.txt