文件名称:myclock
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用Verilog HDL设计一个数字时钟，显示时分秒，日期。其中有一个信号键控制显示时钟还是日期。-Using Verilog HDL design a digital clock display minutes and seconds, date. A signal to control the display clock or date.
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下载文件列表
myclock\myclock.qpf
.......\myclock.qsf
.......\myclock.map.rpt
.......\myclock.flow.rpt
.......\myclock.map.eqn
.......\myclock.fit.eqn
.......\myclock.pin
.......\myclock.fit.rpt
.......\myclock.sof
.......\myclock.pof
.......\myclock.asm.rpt
.......\myclock.tan.summary
.......\myclock.tan.rpt
.......\myclock.done
.......\myclock.vwf
.......\myclock.sim.rpt
.......\sim.cfg
.......\myclock.qws
.......\cmp_state.ini
.......\myclock.cdf
.......\myclock.v
.......\db\myclock.sim.qmsg
.......\..\myclock.db_info
.......\..\myclock-sim.vwf
.......\..\myclock.sim.hdb
.......\..\myclock.sim.rdb
.......\..\myclock_cmp.qrpt
.......\..\myclock.hif
.......\..\myclock_hier_info
.......\..\myclock_syn_hier_info
.......\..\myclock.icc
.......\..\myclock_sim.qrpt
.......\..\myclock.fit.qmsg
.......\..\myclock.asm.qmsg
.......\..\myclock.tan.qmsg
.......\..\myclock.myclock.sld_design_entry.sci
.......\..\myclock.map.qmsg
.......\..\myclock.csf.qmsg
.......\..\myclock.rtlv_sg.cdb
.......\..\myclock.rtlv.hdb
.......\..\myclock.rtlv_sg_swap.cdb
.......\..\myclock.pre_map.hdb
.......\..\myclock.sgdiff.cdb
.......\..\myclock.sgdiff.hdb
.......\..\myclock.project.hdb
.......\..\myclock.map.cdb
.......\..\myclock.map.hdb
.......\..\myclock.cmp.rdb
.......\..\myclock.cmp.tdb
.......\..\myclock.cmp.ddb
.......\..\myclock.cmp.cdb
.......\..\myclock.signalprobe.cdb
.......\..\myclock.cmp.hdb
.......\db
myclock