文件名称:addr_rtl
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利用Verilog HDL编写程序
利用assign语句实现加法器-Use Verilog HDL to write programs
Using the assign statement adder
利用assign语句实现加法器-Use Verilog HDL to write programs
Using the assign statement adder
(系统自动生成,下载前可以参看下载内容)
下载文件列表
addr_rtl
........\addr_rtl.cr.mti
........\addr_rtl.mpf
........\addr_rtl.v
........\addr_rtl.v.bak
........\addr_rtl.xml
........\addr_rtl_tb.v
........\addr_rtl_tb.v.bak
........\transcript
........\vsim.wlf
........\work
........\....\_info
........\....\_temp
........\....\_vmake
........\....\addr_rtl
........\....\........\_primary.dat
........\....\........\_primary.dbs
........\....\........\_primary.vhd
........\....\........\verilog.asm
........\....\........\verilog.rw
........\....\addr_rtl_tb
........\....\...........\_primary.dat
........\....\...........\_primary.dbs
........\....\...........\_primary.vhd
........\....\...........\verilog.asm
........\....\...........\verilog.rw