文件名称:s17_flash

  • 所属分类:
  • 其他小程序
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2013-05-07
  • 文件大小:
  • 396kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • guans*****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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关于flash的演示的代码,用的是verilog语言-failed to translate
(系统自动生成,下载前可以参看下载内容)

下载文件列表





s17_flash\project\flash.v

.........\.......\flash_test.ucf

.........\.......\..s_test\device_usage_statistics.html

.........\.......\........\flash.v

.........\.......\........\flash_test.ucf

.........\.......\........\flash_wr.bgn

.........\.......\........\flash_wr.bit

.........\.......\........\flash_wr.bld

.........\.......\........\flash_wr.cmd_log

.........\.......\........\flash_wr.drc

.........\.......\........\flash_wr.lso

.........\.......\........\flash_wr.ncd

.........\.......\........\flash_wr.ngc

.........\.......\........\flash_wr.ngd

.........\.......\........\flash_wr.ngr

.........\.......\........\flash_wr.pad

.........\.......\........\flash_wr.par

.........\.......\........\flash_wr.pcf

.........\.......\........\flash_wr.prj

.........\.......\........\flash_wr.ptwx

.........\.......\........\flash_wr.stx

.........\.......\........\flash_wr.syr

.........\.......\........\flash_wr.twr

.........\.......\........\flash_wr.twx

.........\.......\........\flash_wr.unroutes

.........\.......\........\flash_wr.ut

.........\.......\........\flash_wr.xpi

.........\.......\........\flash_wr.xst

.........\.......\........\flash_wr_guide.ncd

.........\.......\........\flash_wr_map.map

.........\.......\........\flash_wr_map.mrp

.........\.......\........\flash_wr_map.ncd

.........\.......\........\flash_wr_map.ngm

.........\.......\........\flash_wr_map.xrpt

.........\.......\........\flash_wr_ngdbuild.xrpt

.........\.......\........\flash_wr_pad.csv

.........\.......\........\flash_wr_pad.txt

.........\.......\........\flash_wr_par.xrpt

.........\.......\........\flash_wr_prev_built.ngd

.........\.......\........\flash_wr_summary.html

.........\.......\........\flash_wr_summary.xml

.........\.......\........\flash_wr_usage.xml

.........\.......\........\flash_wr_xst.xrpt

.........\.......\........\fls_test.gise

.........\.......\........\fls_test.ise

.........\.......\........\fls_test.ntrc_log

.........\.......\........\fls_test.xise

.........\.......\........\........_xdb\cst.xbcd

.........\.......\........\............\tmp\ise\version

.........\.......\........\............\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject

.........\.......\........\............\...\...\............\..................\.........\HDProject_StrTbl

.........\.......\........\............\...\...\............\..................\__stored_object_table__

.........\.......\........\............\...\...\............\PnAutoRun\Scripts\RunOnce_tcl

.........\.......\........\............\...\...\............\.........\.......\RunOnce_tcl_StrTbl

.........\.......\........\............\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main

.........\.......\........\............\...\...\............\................\................\dpm_project_main_StrTbl

.........\.......\........\............\...\...\............\................Gui\CViewSelector

.........\.......\........\............\...\...\............\...................\CViewSelector_StrTbl

.........\.......\........\............\...\...\............\...................\File-SynthesisOnly

.........\.......\........\............\...\...\............\...................\File-SynthesisOnly_StrTbl

.........\.......\........\............\...\...\............\...................\Library-SynthesisOnly

.........\.......\........\............\...\...\............\...................\Library-SynthesisOnly_StrTbl

.........\.......\........\............\...\...\............\...................\Process-SynthesisOnly-

.........\.......\........\............\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG

.........\.......\........\............\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl

.........\.......\........\............\...\...\............\...................\Process-SynthesisOnly-_StrTbl

.........\.......\........\............\...\...\............\...................\Source-SynthesisOnly-AutoCompile

.........\.......\........\............\...\...\............\...................\Source-Synt

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