文件名称:DIVISION
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用verilog HDL语言编写的实现两个数相除的例程，在DE-70开发板上实现。-Verilog HDL language routines divide two numbers in the DE-70 development board to achieve.
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下载文件列表
DIVISION\db\div.cbx.xml
........\..\div.cmp.rdb
........\..\div.cmp_merge.kpt
........\..\div.db_info
........\..\div.eco.cdb
........\..\div.eda.qmsg
........\..\div.hier_info
........\..\div.hif
........\..\div.lpc.html
........\..\div.lpc.rdb
........\..\div.lpc.txt
........\..\div.map.bpm
........\..\div.map.cdb
........\..\div.map.ecobp
........\..\div.map.hdb
........\..\div.map.kpt
........\..\div.map.logdb
........\..\div.map.qmsg
........\..\div.map_bb.cdb
........\..\div.map_bb.hdb
........\..\div.map_bb.logdb
........\..\div.pre_map.cdb
........\..\div.pre_map.hdb
........\..\div.rtlv.hdb
........\..\div.rtlv_sg.cdb
........\..\div.rtlv_sg_swap.cdb
........\..\div.sgdiff.cdb
........\..\div.sgdiff.hdb
........\..\div.sld_design_entry.sci
........\..\div.sld_design_entry_dsc.sci
........\..\div.syn_hier_info
........\..\div.tis_db_list.ddb
........\..\div.tmw_info
........\..\prev_cmp_div.eda.qmsg
........\..\prev_cmp_div.map.qmsg
........\..\prev_cmp_div.qmsg
........\div.done
........\div.eda.rpt
........\div.flow.rpt
........\div.map.rpt
........\div.map.summary
........\div.qpf
........\div.qsf
........\div.qws
........\div.v
........\div.v.bak
........\div_nativelink_simulation.rpt
........\incremental_db\compiled_partitions\div.root_partition.map.atm
........\..............\...................\div.root_partition.map.dpi
........\..............\...................\div.root_partition.map.hdbx
........\..............\...................\div.root_partition.map.kpt
........\..............\README
........\simulation\modelsim\div.vt
........\..........\........\div.vt.bak
........\..........\........\div_run_msim_rtl_verilog.do
........\..........\........\div_run_msim_rtl_verilog.do.bak
........\..........\........\modelsim.ini
........\..........\........\msim_transcript
........\..........\........\rtl_work\div\verilog.psm
........\..........\........\........\...\_primary.dat
........\..........\........\........\...\_primary.dbs
........\..........\........\........\...\_primary.vhd
........\..........\........\........\..._vlg_tst\verilog.psm
........\..........\........\........\...........\_primary.dat
........\..........\........\........\...........\_primary.dbs
........\..........\........\........\...........\_primary.vhd
........\..........\........\........\_info
........\..........\........\........\_vmake
........\..........\........\vsim.wlf
........\..........\........\rtl_work\div
........\..........\........\........\div_vlg_tst
........\..........\........\........\_temp
........\..........\........\rtl_work
........\incremental_db\compiled_partitions
........\simulation\modelsim
........\db
........\incremental_db
........\simulation
DIVISION