文件名称:PLL
下载
别用迅雷、360浏览器下载。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
quartus II中IP核的使用案例，在程序里边调用了PLL核进行时钟的管理。-Quartus II IP core use cases, called in the program inside the PLL core clock management.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
PLL\db\pll_prj.cbx.xml
...\..\pll_prj.cmp.hdb
...\..\pll_prj.cmp.rdb
...\..\pll_prj.cmp_merge.kpt
...\..\pll_prj.db_info
...\..\pll_prj.eco.cdb
...\..\pll_prj.eda.qmsg
...\..\pll_prj.hier_info
...\..\pll_prj.hif
...\..\pll_prj.lpc.html
...\..\pll_prj.lpc.rdb
...\..\pll_prj.lpc.txt
...\..\pll_prj.map.bpm
...\..\pll_prj.map.cdb
...\..\pll_prj.map.ecobp
...\..\pll_prj.map.hdb
...\..\pll_prj.map.kpt
...\..\pll_prj.map.logdb
...\..\pll_prj.map.qmsg
...\..\pll_prj.map_bb.cdb
...\..\pll_prj.map_bb.hdb
...\..\pll_prj.map_bb.logdb
...\..\pll_prj.pre_map.cdb
...\..\pll_prj.pre_map.hdb
...\..\pll_prj.rtlv.hdb
...\..\pll_prj.rtlv_sg.cdb
...\..\pll_prj.rtlv_sg_swap.cdb
...\..\pll_prj.sgdiff.cdb
...\..\pll_prj.sgdiff.hdb
...\..\pll_prj.sld_design_entry.sci
...\..\pll_prj.sld_design_entry_dsc.sci
...\..\pll_prj.syn_hier_info
...\..\pll_prj.tis_db_list.ddb
...\..\pll_prj.tmw_info
...\..\prev_cmp_pll_prj.map.qmsg
...\..\prev_cmp_pll_prj.qmsg
...\incremental_db\compiled_partitions\pll_prj.root_partition.map.atm
...\..............\...................\pll_prj.root_partition.map.dpi
...\..............\...................\pll_prj.root_partition.map.hdbx
...\..............\...................\pll_prj.root_partition.map.kpt
...\..............\...................\pll_prj.root_partition.merge_hb.atm
...\..............\README
...\pll_ctrl.bsf
...\pll_ctrl.ppf
...\pll_ctrl.qip
...\pll_ctrl.v
...\pll_ctrl_bb.v
...\pll_ctrl_inst.v
...\pll_ctrl_wave0.jpg
...\pll_ctrl_waveforms.html
...\pll_prj.done
...\pll_prj.eda.rpt
...\pll_prj.flow.rpt
...\pll_prj.map.rpt
...\pll_prj.map.summary
...\pll_prj.qpf
...\pll_prj.qsf
...\pll_prj.qws
...\pll_prj.v
...\pll_prj_nativelink_simulation.rpt
...\simulation\modelsim\modelsim.ini
...\..........\........\msim_transcript
...\..........\........\pll_prj.vt
...\..........\........\pll_prj.vt.bak
...\..........\........\pll_prj_run_msim_rtl_verilog.do
...\..........\........\pll_prj_run_msim_rtl_verilog.do.bak
...\..........\........\rtl_work\pll_ctrl\verilog.psm
...\..........\........\........\........\_primary.dat
...\..........\........\........\........\_primary.dbs
...\..........\........\........\........\_primary.vhd
...\..........\........\........\....prj\verilog.psm
...\..........\........\........\.......\_primary.dat
...\..........\........\........\.......\_primary.dbs
...\..........\........\........\.......\_primary.vhd
...\..........\........\........\......._vlg_tst\verilog.psm
...\..........\........\........\...............\_primary.dat
...\..........\........\........\...............\_primary.dbs
...\..........\........\........\...............\_primary.vhd
...\..........\........\........\_info
...\..........\........\........\_vmake
...\..........\........\vsim.wlf
...\..........\........\rtl_work\pll_ctrl
...\..........\........\........\pll_prj
...\..........\........\........\pll_prj_vlg_tst
...\..........\........\........\_temp
...\..........\........\rtl_work
...\incremental_db\compiled_partitions
...\simulation\modelsim
...\db
...\incremental_db
...\simulation
PLL