文件名称:sockit_owm_latest.tar
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1-wire master written in Verilog HDL, ready for integration into a FPGA
or ASIC based SoC. A port of the 1-wire Public Domain Kit (version 3.10r2) from Maxim is also provided, with all the code required for integration into the Altera development environment.
or ASIC based SoC. A port of the 1-wire Public Domain Kit (version 3.10r2) from Maxim is also provided, with all the code required for integration into the Altera development environment.
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101259384sockit_owm_latest.tar