文件名称:RD1088_rev01.2
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FPGA或CPLD读取SD卡的IP核，基于wishbone接口，支持SDHC2.0，包含了使用说明，为Verilog语言编写-FPGA or CPLD reads the SD card IP core, based on the wishbone interface, support SDHC2.0, contains instructions for the Verilog language
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下载文件列表
RD1088_rev01.2
..............\Docs
..............\....\rd1088.pdf
..............\....\rd1088_readme.txt
..............\Project
..............\.......\sd_card_controller.lpf
..............\.......\SD_controller_top_tb.udo_example
..............\simulation
..............\..........\verilog
..............\..........\.......\rtl_verilog.do
..............\..........\.......\timing_verilog.do
..............\Source
..............\......\verilog
..............\......\.......\SD_Bd.v
..............\......\.......\SD_cmd_master.v
..............\......\.......\SD_cmd_serial_host.v
..............\......\.......\SD_controller_top.v
..............\......\.......\SD_controller_wb.v
..............\......\.......\SD_crc_16.v
..............\......\.......\SD_crc_7.v
..............\......\.......\SD_data_host.v
..............\......\.......\SD_data_master.v
..............\......\.......\SD_defines.v
..............\......\.......\SD_FIFO_RX_Filler.v
..............\......\.......\SD_FIFO_TX_Filler.v
..............\......\.......\smii_rx_fifo.v
..............\......\.......\smii_tx_fifo.v
..............\Testbench
..............\.........\verilog
..............\.........\.......\FLASH.txt
..............\.........\.......\log
..............\.........\.......\...\eth_tb_host.log
..............\.........\.......\...\eth_tb_phy.log
..............\.........\.......\...\eth_tb_wb_m_mon.log
..............\.........\.......\...\eth_tb_wb_s_mon.log
..............\.........\.......\...\sdc_tb.log
..............\.........\.......\...\sd_model.log
..............\.........\.......\...\sd_tb_memory.log
..............\.........\.......\sdModel.v
..............\.........\.......\SD_controller_top_tb.v
..............\.........\.......\wb_bus_mon.v
..............\.........\.......\wb_master32.v
..............\.........\.......\wb_master_behavioral.v
..............\.........\.......\wb_memory.txt
..............\.........\.......\wb_model_defines.v
..............\.........\.......\wb_slave_behavioral.v