文件名称:USB2.0IP
下载
别用迅雷、360浏览器下载。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
usb2.0的IP核，对于USB接口通信的FPGA设计有很大帮助，对于接口硬件的控制更为灵活。
有详尽的USB2.0协议说明-usb2.0 IP core for FPGA design of the USB interface communication, more flexible control interface hardware.
Detailed USB2.0 protocol descr iption
有详尽的USB2.0协议说明-usb2.0 IP core for FPGA design of the USB interface communication, more flexible control interface hardware.
Detailed USB2.0 protocol descr iption
(系统自动生成,下载前可以参看下载内容)
下载文件列表
USB2.0的IP核（详细verilog源码和文档）\usb_funct\bench\CVS\Entries
.....................................\.........\.....\...\Repository
.....................................\.........\.....\...\Root
.....................................\.........\.....\verilog\CVS\Entries
.....................................\.........\.....\.......\...\Repository
.....................................\.........\.....\.......\...\Root
.....................................\.........\doc\CVS\Entries
.....................................\.........\...\...\Repository
.....................................\.........\...\...\Root
.....................................\.........\...\README.txt
.....................................\.........\...\STATUS.txt
.....................................\.........\...\usb_doc.pdf
.....................................\.........\rtl\CVS\Entries
.....................................\.........\...\...\Repository
.....................................\.........\...\...\Root
.....................................\.........\...\verilog\CVS\Entries
.....................................\.........\...\.......\...\Repository
.....................................\.........\...\.......\...\Root
.....................................\.........\...\.......\usbf_crc16.v
.....................................\.........\...\.......\usbf_crc5.v
.....................................\.........\...\.......\usbf_defines.v
.....................................\.........\...\.......\usbf_ep_rf.v
.....................................\.........\...\.......\usbf_ep_rf_dummy.v
.....................................\.........\...\.......\usbf_idma.v
.....................................\.........\...\.......\usbf_mem_arb.v
.....................................\.........\...\.......\usbf_pa.v
.....................................\.........\...\.......\usbf_pd.v
.....................................\.........\...\.......\usbf_pe.v
.....................................\.........\...\.......\usbf_pl.v
.....................................\.........\...\.......\usbf_rf.v
.....................................\.........\...\.......\usbf_top.v
.....................................\.........\...\.......\usbf_utmi_if.v
.....................................\.........\...\.......\usbf_utmi_ls.v
.....................................\.........\...\.......\usbf_wb.v
.....................................\.........\sim\CVS\Entries
.....................................\.........\...\...\Repository
.....................................\.........\...\...\Root
.....................................\.........\...\rtl_sim\bin\CVS\Entries
.....................................\.........\...\.......\...\...\Repository
.....................................\.........\...\.......\...\...\Root
.....................................\.........\...\.......\CVS\Entries
.....................................\.........\...\.......\...\Repository
.....................................\.........\...\.......\...\Root
.....................................\.........\...\.......\run\CVS\Entries
.....................................\.........\...\.......\...\...\Repository
.....................................\.........\...\.......\...\...\Root
.....................................\.........\.yn\bin\comp.dc
.....................................\.........\...\...\CVS\Entries
.....................................\.........\...\...\...\Repository
.....................................\.........\...\...\...\Root
.....................................\.........\...\...\design_spec.dc
.....................................\.........\...\...\lib_spec.dc
.....................................\.........\...\...\read.dc
.....................................\.........\...\CVS\Entries
.....................................\.........\...\...\Repository
.....................................\.........\...\...\Root
.....................................\.........\...\log\CVS\Entries
.....................................\.........\...\...\...\Repository
.....................................\.........\...\...\