文件名称:SMBus_Controller
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基于MAX系列CPLD的SMBUS控制器工程文件。代码为VHDL代码-The the SMBUS controller works based on the MAX series CPLDs file. Code for VHDL code
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下载文件列表
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example\code\arbitration.v
..................................................\....\bus_idle_detect.v
..................................................\....\mod__crc.v
..................................................\....\op_stage.v
..................................................\....\oscillator.v
..................................................\....\smbus_controller.v
..................................................\modelsim\arbitration.v
..................................................\........\bus_idle_detect.v
..................................................\........\mod__crc.v
..................................................\........\op_stage.v
..................................................\........\oscillator.v
..................................................\........\smbus_controller.cr.mti
..................................................\........\smbus_controller.mpf
..................................................\........\smbus_controller.v
..................................................\........\transcript
..................................................\........\tst_bnch.v
..................................................\........\vsim.wlf
..................................................\........\wave.bmp
..................................................\........\wave.do
..................................................\........\.ork\arbitration\verilog.psm
..................................................\........\....\...........\_primary.dat
..................................................\........\....\...........\_primary.vhd
..................................................\........\....\bus_idle_detect\verilog.psm
..................................................\........\....\...............\_primary.dat
..................................................\........\....\...............\_primary.vhd
..................................................\........\....\clkgen_low_extend_detect\verilog.psm
..................................................\........\....\........................\_primary.dat
..................................................\........\....\........................\_primary.vhd
..................................................\........\....\fsm\verilog.psm
..................................................\........\....\...\_primary.dat
..................................................\........\....\...\_primary.vhd
..................................................\........\....\mod_crc\verilog.psm
..................................................\........\....\.......\_primary.dat
..................................................\........\....\.......\_primary.vhd
..................................................\........\....\oscillator\verilog.psm
..................................................\........\....\..........\_primary.dat
..................................................\........\....\..........\_primary.vhd
..................................................\........\....\.........._altufm_osc_7p3\verilog.psm
..................................................\........\....\.........................\_primary.dat
..................................................\........\....\.........................\_primary.vhd
..................................................\........\....\.utput_stage\verilog.psm
..................................................\........\....\............\_primary.dat
..................................................\........\....\............\_primary.vhd
..................................................\........\....\pec\verilog.psm
..................................................\........\....\...\_primary.dat
..................................................\........\....\...\_primary.vhd
..................................................\........\....\.iso\verilog.psm
..................................................\........\....\....\_primary.dat
..................................................\........\....\....\_primary.vhd
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