文件名称:xapp635
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FPGA与 TS20x LINK接口通讯实现源码-FPGA to achieve with TS20x LINK interface communication source
(系统自动生成,下载前可以参看下载内容)
下载文件列表
xapp635\left_right_io_placement.ppt
.......\readme.txt
.......\vhdl
.......\....\simulation
.......\....\..........\tb_top_4_128.vhd
.......\....\..........\tb_top_4_128_slow.vhd
.......\....\..........\top_4_128.do
.......\....\..........\top_4_128_slow.do
.......\....\design_files
.......\....\............\rx_4_128_left.vhd
.......\....\............\rx_4_128_right.vhd
.......\....\............\serdes_4b_4to1.vhd
.......\....\............\top_4_128_left_rx.vhd
.......\....\............\top_4_128_left_rx_slow.vhd
.......\....\............\top_4_128_right_rx.vhd
.......\....\............\tx_4_128.vhd
.......\....\............\tx_4_128_slow.vhd
.......\....\constraints
.......\....\...........\top_4_128_left_rx.ucf
.......\....\...........\top_4_128_left_rx_slow.ucf
.......\....\...........\top_4_128_right_rxr.ucf
.......\verilog
.......\.......\simulation
.......\.......\..........\tb_top_4_128.v
.......\.......\..........\tb_top_4_128_slow.v
.......\.......\..........\top_4_128.do
.......\.......\..........\top_4_128_slow.do
.......\.......\design_files
.......\.......\............\rx_4_128_left.v
.......\.......\............\rx_4_128_right.v
.......\.......\............\serdes_4b_4to1.v
.......\.......\............\top_4_128_left_rx.v
.......\.......\............\top_4_128_left_rx_slow.v
.......\.......\............\top_4_128_right_rx.v
.......\.......\............\tx_4_128.v
.......\.......\............\tx_4_128_slow.v
.......\.......\constraints
.......\.......\...........\top_4_128_left_rx.ucf
.......\.......\...........\top_4_128_left_rx_slow.ucf
.......\.......\...........\top_4_128_right_rx.ucf
xapp635