文件名称:BitStream2SPIAdapter
下载
别用迅雷、360浏览器下载。
如迅雷强制弹出,可右键点击选“另存为”。
失败请重下,重下不扣分。
如迅雷强制弹出,可右键点击选“另存为”。
失败请重下,重下不扣分。
介绍说明--下载内容均来自于网络,请自行研究使用
verilog code for bit stream adapters
(系统自动生成,下载前可以参看下载内容)
下载文件列表
BitStream2SPIAdapter
....................\BarkerCodeDecision.v
....................\BarkerCodeDecision.v.bak
....................\BitStream2SPIAdapter.v
....................\BitStream2SPIAdapter.v.bak
....................\EndFlagDecision.v
....................\EndFlagDecision.v.bak
....................\RSTGenerator.v
....................\RSTGenerator.v.bak
....................\ShiftRegController.v
....................\ShiftRegController.v.bak
....................\SPIController.v
....................\SPIController.v.bak
....................\testadapter.cr.mti
....................\testadapter.mpf
....................\testadapter.v
....................\testadapter.v.bak
....................\TotalSystemController.v
....................\TotalSystemController.v.bak
....................\transcript
....................\vsim.wlf
....................\wave.do
....................\work
....................\....\_info
....................\....\@barker@code@decision
....................\....\.....................\verilog.asm
....................\....\.....................\_primary.dat
....................\....\.....................\_primary.vhd
....................\....\@bit@stream2@s@p@i@adapter
....................\....\..........................\verilog.asm
....................\....\..........................\_primary.dat
....................\....\..........................\_primary.vhd
....................\....\@end@flag@decision
....................\....\..................\verilog.asm
....................\....\..................\_primary.dat
....................\....\..................\_primary.vhd
....................\....\@r@s@t@generator
....................\....\................\verilog.asm
....................\....\................\_primary.dat
....................\....\................\_primary.vhd
....................\....\@s@p@i@controller
....................\....\.................\verilog.asm
....................\....\.................\_primary.dat
....................\....\.................\_primary.vhd
....................\....\@shift@reg@controller
....................\....\.....................\verilog.asm
....................\....\.....................\_primary.dat
....................\....\.....................\_primary.vhd
....................\....\@total@system@controller
....................\....\........................\verilog.asm
....................\....\........................\_primary.dat
....................\....\........................\_primary.vhd
....................\....\testadapter
....................\....\...........\verilog.asm
....................\....\...........\_primary.dat
....................\....\...........\_primary.vhd
....................\....\_opt
....................\....\....\work_@barker@code@decision_fast.dt2
....................\....\....\work_@bit@stream2@s@p@i@adapter_fast.dt2
....................\....\....\work_@end@flag@decision_fast.dt2
....................\....\....\work_@r@s@t@generator_fast.dt2
....................\....\....\work_@s@p@i@controller_fast.dt2
....................\....\....\work_@shift@reg@controller_fast.dt2
....................\....\....\work_@total@system@controller_fast.dt2
....................\....\....\work_testadapter_fast.asm
....................\....\....\work_testadapter_fast.dt2
....................\....\....\work__info
....................\....\....\_deps
....................\....\_temp