文件名称:100powertips
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these are the source codes for the book " 100 power tips for FPGA designers"
(系统自动生成,下载前可以参看下载内容)
下载文件列表
100powertips\src_book\13.14.15.coding\rtl\coding_style.v
............\........\...............\...\simple.v
............\........\...............\...\synth_support.v
............\........\...............\...\tb.v
............\........\...............\rtl
............\........\...............\synth\isim.cmd
............\........\...............\.....\sim1.wcfg
............\........\...............\.....\sim2.wcfg
............\........\...............\.....\synth.xise
............\........\...............\.....\synth_support.lso
............\........\...............\synth
............\........\13.14.15.coding
............\........\.6.inference\rtl\inference.v
............\........\............\rtl
............\........\............\synth\inference.lso
............\........\............\.....\inference.ptwx
............\........\............\.....\inference.stx
............\........\............\.....\inference.unroutes
............\........\............\.....\inference.xpi
............\........\............\.....\inference_map.mrp
............\........\............\.....\netgen\map\inference_map.sdf
............\........\............\.....\......\...\inference_map.v
............\........\............\.....\......\map
............\........\............\.....\......\synthesis\inference_synthesis.v
............\........\............\.....\......\synthesis
............\........\............\.....\netgen
............\........\............\.....\synth.xise
............\........\............\synth
............\........\16.inference
............\........\.7.mixed_verilog_vhdl\rtl\counter.vhd
............\........\.....................\...\tb.v
............\........\.....................\...\top.v
............\........\.....................\rtl
............\........\.....................\synth\isim.cmd
............\........\.....................\.....\synth.xise
............\........\.....................\.....\top.lso
............\........\.....................\.....\top.ptwx
............\........\.....................\.....\top.stx
............\........\.....................\.....\top_map.mrp
............\........\.....................\synth
............\........\17.mixed_verilog_vhdl
............\........\.8.verilog\rtl\verilog2001.v
............\........\..........\rtl
............\........\..........\synth\synth.xise
............\........\..........\.....\verilog2001.lso
............\........\..........\.....\verilog2001.stx
............\........\..........\.....\verilog2001_map.mrp
............\........\..........\synth
............\........\18.verilog
............\........\20.21.clocking\cores\.lso
............\........\..............\.....\blk_mem.v
............\........\..............\.....\blk_mem.xco
............\........\..............\.....\clka_mmcm.v
............\........\..............\.....\clka_mmcm.xco
............\........\..............\.....\clk_dcm.v
............\........\..............\.....\clk_dcm.xco
............\........\..............\.....\clk_mmcm.v
............\........\..............\.....\clk_mmcm.xco
............\........\..............\.....\coregen.cgp
............\........\..............\cores
............\........\..............\rtl\clock_dcm.v
............\........\..............\...\clock_inference.v
............\........\..............\...\clock_mmcm.v
............\........\..............\...\clock_schemes.v
............\........\..............\...\timing_analyzer.v
............\........\..............\rtl
............\........\..............\synth\clock_dcm.lso
............\........\..............\.....\clock_dcm.ptwx
............\........\..............\.....\clock_dcm.stx
............\........\..............\.....\clock_dcm.ucf
............\........\..............\.....\clock_dcm.unroutes
............\........\..............\.....\clock_dcm.xpi
............\........\..............\.....\clock_dcm_map.mrp
............\........\..............\.....\clock_inference.ptwx
............\........\..............\.....\clock_inference.ucf
............\........\..............\.....\clock_inference.
............\........\...............\...\simple.v
............\........\...............\...\synth_support.v
............\........\...............\...\tb.v
............\........\...............\rtl
............\........\...............\synth\isim.cmd
............\........\...............\.....\sim1.wcfg
............\........\...............\.....\sim2.wcfg
............\........\...............\.....\synth.xise
............\........\...............\.....\synth_support.lso
............\........\...............\synth
............\........\13.14.15.coding
............\........\.6.inference\rtl\inference.v
............\........\............\rtl
............\........\............\synth\inference.lso
............\........\............\.....\inference.ptwx
............\........\............\.....\inference.stx
............\........\............\.....\inference.unroutes
............\........\............\.....\inference.xpi
............\........\............\.....\inference_map.mrp
............\........\............\.....\netgen\map\inference_map.sdf
............\........\............\.....\......\...\inference_map.v
............\........\............\.....\......\map
............\........\............\.....\......\synthesis\inference_synthesis.v
............\........\............\.....\......\synthesis
............\........\............\.....\netgen
............\........\............\.....\synth.xise
............\........\............\synth
............\........\16.inference
............\........\.7.mixed_verilog_vhdl\rtl\counter.vhd
............\........\.....................\...\tb.v
............\........\.....................\...\top.v
............\........\.....................\rtl
............\........\.....................\synth\isim.cmd
............\........\.....................\.....\synth.xise
............\........\.....................\.....\top.lso
............\........\.....................\.....\top.ptwx
............\........\.....................\.....\top.stx
............\........\.....................\.....\top_map.mrp
............\........\.....................\synth
............\........\17.mixed_verilog_vhdl
............\........\.8.verilog\rtl\verilog2001.v
............\........\..........\rtl
............\........\..........\synth\synth.xise
............\........\..........\.....\verilog2001.lso
............\........\..........\.....\verilog2001.stx
............\........\..........\.....\verilog2001_map.mrp
............\........\..........\synth
............\........\18.verilog
............\........\20.21.clocking\cores\.lso
............\........\..............\.....\blk_mem.v
............\........\..............\.....\blk_mem.xco
............\........\..............\.....\clka_mmcm.v
............\........\..............\.....\clka_mmcm.xco
............\........\..............\.....\clk_dcm.v
............\........\..............\.....\clk_dcm.xco
............\........\..............\.....\clk_mmcm.v
............\........\..............\.....\clk_mmcm.xco
............\........\..............\.....\coregen.cgp
............\........\..............\cores
............\........\..............\rtl\clock_dcm.v
............\........\..............\...\clock_inference.v
............\........\..............\...\clock_mmcm.v
............\........\..............\...\clock_schemes.v
............\........\..............\...\timing_analyzer.v
............\........\..............\rtl
............\........\..............\synth\clock_dcm.lso
............\........\..............\.....\clock_dcm.ptwx
............\........\..............\.....\clock_dcm.stx
............\........\..............\.....\clock_dcm.ucf
............\........\..............\.....\clock_dcm.unroutes
............\........\..............\.....\clock_dcm.xpi
............\........\..............\.....\clock_dcm_map.mrp
............\........\..............\.....\clock_inference.ptwx
............\........\..............\.....\clock_inference.ucf
............\........\..............\.....\clock_inference.