文件名称:timer_ip_core
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timer ip core 8 bit, verilog simulation and coding
(系统自动生成,下载前可以参看下载内容)
下载文件列表
timer_ip_core\work\top\_primary.dat
.............\....\...\_primary.vhd
.............\....\...\verilog.psm
.............\....\top
.............\....\_temp
.............\....\ip_decoder\_primary.dat
.............\....\..........\_primary.vhd
.............\....\..........\verilog.psm
.............\....\ip_decoder
.............\....\test_top\_primary.dat
.............\....\........\_primary.vhd
.............\....\........\verilog.psm
.............\....\test_top
.............\....\read_write\_primary.dat
.............\....\..........\_primary.vhd
.............\....\..........\verilog.psm
.............\....\read_write
.............\....\select_clk\_primary.dat
.............\....\..........\_primary.vhd
.............\....\..........\verilog.psm
.............\....\select_clk
.............\....\control_logic\_primary.dat
.............\....\.............\_primary.vhd
.............\....\.............\verilog.psm
.............\....\control_logic
.............\....\read_write_control\_primary.dat
.............\....\..................\_primary.vhd
.............\....\..................\verilog.psm
.............\....\read_write_control
.............\....\module_test_ip_decoder\_primary.dat
.............\....\......................\_primary.vhd
.............\....\......................\verilog.psm
.............\....\module_test_ip_decoder
.............\....\external_clock_gen\_primary.dat
.............\....\..................\_primary.vhd
.............\....\..................\verilog.psm
.............\....\external_clock_gen
.............\....\cpu_model\_primary.dat
.............\....\.........\_primary.vhd
.............\....\.........\verilog.psm
.............\....\cpu_model
.............\....\_info
.............\work
.............\transcript
.............\select_clk.v
.............\top.v
.............\control_logic.v
.............\select_clk.v.bak
.............\external_clock_gen.v.bak
.............\vsim.wlf
.............\cpu_model.v
.............\top.v.bak
.............\read_write.v.bak
.............\modelsim.ini
.............\cpu_model.v.bak
.............\read_write.v
.............\external_clock_gen.v
timer_ip_core
.............\....\...\_primary.vhd
.............\....\...\verilog.psm
.............\....\top
.............\....\_temp
.............\....\ip_decoder\_primary.dat
.............\....\..........\_primary.vhd
.............\....\..........\verilog.psm
.............\....\ip_decoder
.............\....\test_top\_primary.dat
.............\....\........\_primary.vhd
.............\....\........\verilog.psm
.............\....\test_top
.............\....\read_write\_primary.dat
.............\....\..........\_primary.vhd
.............\....\..........\verilog.psm
.............\....\read_write
.............\....\select_clk\_primary.dat
.............\....\..........\_primary.vhd
.............\....\..........\verilog.psm
.............\....\select_clk
.............\....\control_logic\_primary.dat
.............\....\.............\_primary.vhd
.............\....\.............\verilog.psm
.............\....\control_logic
.............\....\read_write_control\_primary.dat
.............\....\..................\_primary.vhd
.............\....\..................\verilog.psm
.............\....\read_write_control
.............\....\module_test_ip_decoder\_primary.dat
.............\....\......................\_primary.vhd
.............\....\......................\verilog.psm
.............\....\module_test_ip_decoder
.............\....\external_clock_gen\_primary.dat
.............\....\..................\_primary.vhd
.............\....\..................\verilog.psm
.............\....\external_clock_gen
.............\....\cpu_model\_primary.dat
.............\....\.........\_primary.vhd
.............\....\.........\verilog.psm
.............\....\cpu_model
.............\....\_info
.............\work
.............\transcript
.............\select_clk.v
.............\top.v
.............\control_logic.v
.............\select_clk.v.bak
.............\external_clock_gen.v.bak
.............\vsim.wlf
.............\cpu_model.v
.............\top.v.bak
.............\read_write.v.bak
.............\modelsim.ini
.............\cpu_model.v.bak
.............\read_write.v
.............\external_clock_gen.v
timer_ip_core