lab3NHHT\all_mux.v

........\ALU.v

........\ALUstim.v

........\control.v

........\CPU.v

........\CPU.v.bak

........\cpustim.v

........\cpustim.v.bak

........\datamem.v

........\instrmem.v

........\instrmem.v.bak

........\IntrsFetch.v

........\IntrsFetch.v.bak

........\labfinallyNHHT.cr.mti

........\labfinallyNHHT.mpf

........\regfile.v

........\regstim.v

........\test01.out

........\test01_AddiJ.txt

........\test02.out

........\test02_subu.txt

........\test03.out

........\test03_nor.txt

........\test04.out

........\test04_J_Jr.txt

........\test05.out

........\test05_LwSw.txt

........\test06.out

........\test06_bltz.txt

........\test07.out

........\test07_sltu.txt

........\test08.out

........\test08_Forwarding.txt

........\test09.out

........\test09_Sorter.txt

........\vsim.wlf

........\wlft5ea8ff

........\wlftfcshd7

........\wlftg16jiq

........\wlftzhveq5

........\wlftzneya2

........\.ork\@a@l@u\verilog.prw

........\....\......\verilog.psm

........\....\......\_primary.dat

........\....\......\_primary.dbs

........\....\......\_primary.vhd

........\....\......@stimulus\verilog.prw

........\....\...............\verilog.psm

........\....\...............\_primary.dat

........\....\...............\_primary.dbs

........\....\...............\_primary.vhd

........\....\.c@p@u\verilog.prw

........\....\......\verilog.psm

........\....\......\_primary.dat

........\....\......\_primary.dbs

........\....\......\_primary.vhd

........\....\......@stimulus\verilog.prw

........\....\...............\verilog.psm

........\....\...............\_primary.dat

........\....\...............\_primary.dbs

........\....\...............\_primary.vhd

........\....\..oncate\verilog.prw

........\....\........\verilog.psm

........\....\........\_primary.dat

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........\....\........\_primary.vhd

........\....\.d_@f@f\verilog.prw

........\....\.......\verilog.psm

........\....\.......\_primary.dat

........\....\.......\_primary.dbs

........\....\.......\_primary.vhd

........\....\.instr@fetch\verilog.prw

........\....\............\verilog.psm

........\....\............\_primary.dat

........\....\............\_primary.dbs

........\....\............\_primary.vhd

........\....\......uction@mem\verilog.prw

........\....\................\verilog.psm

........\....\................\_primary.dat

........\....\................\_primary.dbs

........\....\................\_primary.vhd

........\....\.reg@file@stimulus\verilog.prw

........\....\..................\verilog.psm

........\....\..................\_primary.dat

........\....\..................\_primary.dbs

........\....\..................\_primary.vhd

........\....\add_1bit\verilog.prw

........\....\........\verilog.psm

........\....\........\_primary.dat

........\....\........\_primary.dbs

........\....\........\_primary.vhd

........\....\....32bit\verilog.prw

........\....\.........\verilog.psm

........\....\.........\_primary.dat

........\....\.........\_primary.dbs

........\....\.........\_primary.vhd

........\....\bit\verilog.prw

........\....\...\verilog.psm

........\....\...\_primary.dat

........\....\...\_primary.dbs