文件名称:FdplllzipP
介绍说明－－下载内容均来自于网络，请自行研究使用
ＦＰＧＡ实现全数字锁相环，运用硬件描述评议议verilog HDL，顶层文件ＤＰＬＬ．Ｖ
-FPGA implementation of DPLL, the use of hardware descr iption council meeting Verilog HDL top-level file DPLL is. V
-FPGA implementation of DPLL, the use of hardware descr iption council meeting Verilog HDL top-level file DPLL is. V
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FdplllzipP\dpll\divfrequency32.v
..........\....\divfrequency32_tp.v
..........\....\divfrequency64.v
..........\....\divfrequency64_tp.v
..........\....\divfrequency8.v
..........\....\divfrequency8_tp.v
..........\....\dpll.v
..........\....\dpll_tp.v
..........\....\maichongjiajian.v
..........\....\maichongjiajian_tp.v
..........\....\moKcounter.v
..........\....\moKcounter_tp.v
..........\....\xorphd.v
..........\....\xorphd_tp.v
..........\dpll
FdplllzipP
..........\....\divfrequency32_tp.v
..........\....\divfrequency64.v
..........\....\divfrequency64_tp.v
..........\....\divfrequency8.v
..........\....\divfrequency8_tp.v
..........\....\dpll.v
..........\....\dpll_tp.v
..........\....\maichongjiajian.v
..........\....\maichongjiajian_tp.v
..........\....\moKcounter.v
..........\....\moKcounter_tp.v
..........\....\xorphd.v
..........\....\xorphd_tp.v
..........\dpll
FdplllzipP