文件名称:project9_freq_counter
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数字频率计的设计,基于VERILOG的数字频率计的设计-Digital frequency plan design, based on the number of VERILOG frequency meter design
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下载文件列表
project9_freq_counter\clk_gen.v
.....................\CONT_10.v
.....................\FPGA应用开发项目_9.ppt
.....................\Freq_counter.pdf
.....................\Freq_counter.v
.....................\Freq_counter_LCD.sof
.....................\Freq_pin.csv
.....................\LCD_1602.pdf
.....................\LCD_1602.v
.....................\PLL50M.ppf
.....................\PLL50M.v
.....................\SEG7_LUT.v
.....................\sem_drive.v
project9_freq_counter
.....................\CONT_10.v
.....................\FPGA应用开发项目_9.ppt
.....................\Freq_counter.pdf
.....................\Freq_counter.v
.....................\Freq_counter_LCD.sof
.....................\Freq_pin.csv
.....................\LCD_1602.pdf
.....................\LCD_1602.v
.....................\PLL50M.ppf
.....................\PLL50M.v
.....................\SEG7_LUT.v
.....................\sem_drive.v
project9_freq_counter