文件名称:djk2
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一个模仿了CPU运算器的VHDL小程序，纠结了好几天，终于搞明白了希望能榜上点忙-A parody of the VHDL program in the CPU power, tangled for several days, finally figured it out hope standings point busy
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下载文件列表
djk2\db\mux_gdc.tdf
....\..\Vhdl1.asm.qmsg
....\..\Vhdl1.cbx.xml
....\..\Vhdl1.cmp.cdb
....\..\Vhdl1.cmp.hdb
....\..\Vhdl1.cmp.logdb
....\..\Vhdl1.cmp.qrpt
....\..\Vhdl1.cmp.rdb
....\..\Vhdl1.cmp.tdb
....\..\Vhdl1.cmp0.ddb
....\..\Vhdl1.dbp
....\..\Vhdl1.db_info
....\..\Vhdl1.eco.cdb
....\..\Vhdl1.eds_overflow
....\..\Vhdl1.fit.qmsg
....\..\Vhdl1.fnsim.cdb
....\..\Vhdl1.fnsim.hdb
....\..\Vhdl1.fnsim.qmsg
....\..\Vhdl1.hier_info
....\..\Vhdl1.hif
....\..\Vhdl1.map.cdb
....\..\Vhdl1.map.hdb
....\..\Vhdl1.map.logdb
....\..\Vhdl1.map.qmsg
....\..\Vhdl1.pre_map.cdb
....\..\Vhdl1.pre_map.hdb
....\..\Vhdl1.psp
....\..\Vhdl1.rtlv.hdb
....\..\Vhdl1.rtlv_sg.cdb
....\..\Vhdl1.rtlv_sg_swap.cdb
....\..\Vhdl1.sgdiff.cdb
....\..\Vhdl1.sgdiff.hdb
....\..\Vhdl1.signalprobe.cdb
....\..\Vhdl1.sim.hdb
....\..\Vhdl1.sim.qmsg
....\..\Vhdl1.sim.qrpt
....\..\Vhdl1.sim.rdb
....\..\Vhdl1.sim.vwf
....\..\Vhdl1.sld_design_entry.sci
....\..\Vhdl1.sld_design_entry_dsc.sci
....\..\Vhdl1.syn_hier_info
....\..\Vhdl1.tan.qmsg
....\talkback\Vhdl1.asm.talkback.xml
....\........\Vhdl1.fit.talkback.xml
....\........\Vhdl1.map.talkback.xml
....\........\Vhdl1.sim.talkback.xml
....\........\Vhdl1.tan.talkback.xml
....\Vhdl1.asm.rpt
....\Vhdl1.done
....\Vhdl1.fit.eqn
....\Vhdl1.fit.rpt
....\Vhdl1.fit.summary
....\Vhdl1.flow.rpt
....\Vhdl1.map.eqn
....\Vhdl1.map.rpt
....\Vhdl1.map.summary
....\Vhdl1.pin
....\Vhdl1.pof
....\Vhdl1.qpf
....\Vhdl1.qsf
....\Vhdl1.qws
....\Vhdl1.sim.rpt
....\Vhdl1.sof
....\Vhdl1.tan.rpt
....\Vhdl1.tan.summary
....\Vhdl1.vhd
....\Vhdl1.vwf
....\Vhdl1_description.txt
....\Waveform1.vwf
....\db
....\talkback
djk2
....\..\Vhdl1.asm.qmsg
....\..\Vhdl1.cbx.xml
....\..\Vhdl1.cmp.cdb
....\..\Vhdl1.cmp.hdb
....\..\Vhdl1.cmp.logdb
....\..\Vhdl1.cmp.qrpt
....\..\Vhdl1.cmp.rdb
....\..\Vhdl1.cmp.tdb
....\..\Vhdl1.cmp0.ddb
....\..\Vhdl1.dbp
....\..\Vhdl1.db_info
....\..\Vhdl1.eco.cdb
....\..\Vhdl1.eds_overflow
....\..\Vhdl1.fit.qmsg
....\..\Vhdl1.fnsim.cdb
....\..\Vhdl1.fnsim.hdb
....\..\Vhdl1.fnsim.qmsg
....\..\Vhdl1.hier_info
....\..\Vhdl1.hif
....\..\Vhdl1.map.cdb
....\..\Vhdl1.map.hdb
....\..\Vhdl1.map.logdb
....\..\Vhdl1.map.qmsg
....\..\Vhdl1.pre_map.cdb
....\..\Vhdl1.pre_map.hdb
....\..\Vhdl1.psp
....\..\Vhdl1.rtlv.hdb
....\..\Vhdl1.rtlv_sg.cdb
....\..\Vhdl1.rtlv_sg_swap.cdb
....\..\Vhdl1.sgdiff.cdb
....\..\Vhdl1.sgdiff.hdb
....\..\Vhdl1.signalprobe.cdb
....\..\Vhdl1.sim.hdb
....\..\Vhdl1.sim.qmsg
....\..\Vhdl1.sim.qrpt
....\..\Vhdl1.sim.rdb
....\..\Vhdl1.sim.vwf
....\..\Vhdl1.sld_design_entry.sci
....\..\Vhdl1.sld_design_entry_dsc.sci
....\..\Vhdl1.syn_hier_info
....\..\Vhdl1.tan.qmsg
....\talkback\Vhdl1.asm.talkback.xml
....\........\Vhdl1.fit.talkback.xml
....\........\Vhdl1.map.talkback.xml
....\........\Vhdl1.sim.talkback.xml
....\........\Vhdl1.tan.talkback.xml
....\Vhdl1.asm.rpt
....\Vhdl1.done
....\Vhdl1.fit.eqn
....\Vhdl1.fit.rpt
....\Vhdl1.fit.summary
....\Vhdl1.flow.rpt
....\Vhdl1.map.eqn
....\Vhdl1.map.rpt
....\Vhdl1.map.summary
....\Vhdl1.pin
....\Vhdl1.pof
....\Vhdl1.qpf
....\Vhdl1.qsf
....\Vhdl1.qws
....\Vhdl1.sim.rpt
....\Vhdl1.sof
....\Vhdl1.tan.rpt
....\Vhdl1.tan.summary
....\Vhdl1.vhd
....\Vhdl1.vwf
....\Vhdl1_description.txt
....\Waveform1.vwf
....\db
....\talkback
djk2