文件名称:edivider
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失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
将数据进行偶数分频，里面有测试文件，可以测试输出的信号-The data divided by an even number, there are test files, you can test the output signal
(系统自动生成,下载前可以参看下载内容)
下载文件列表
edivider\auto_project.ipf
........\auto_project_1.ipf
........\dcm.tfi
........\dcm.v
........\dcm_arwz.ucf
........\DCM_CORE.tfi
........\DCM_CORE.v
........\DCM_CORE_arwz.ucf
........\device_usage_statistics.html
........\edivider.gise
........\edivider.ise
........\edivider.ntrc_log
........\edivider.xise
........\........_xdb\cst.xbcd
........\............\tmp\ise\version
........\............\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
........\............\...\...\............\..................\.........\HDProject_StrTbl
........\............\...\...\............\..................\__stored_object_table__
........\............\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
........\............\...\...\............\.........\.......\RunOnce_tcl_StrTbl
........\............\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
........\............\...\...\............\................\................\dpm_project_main_StrTbl
........\............\...\...\............\................Gui\CSourceProcessView
........\............\...\...\............\...................\CSourceProcessView_StrTbl
........\............\...\...\............\...................\CViewSelector
........\............\...\...\............\...................\CViewSelector_StrTbl
........\............\...\...\............\...................\File-SynthesisOnly
........\............\...\...\............\...................\File-SynthesisOnly_StrTbl
........\............\...\...\............\...................\Library-SynthesisOnly
........\............\...\...\............\...................\Library-SynthesisOnly_StrTbl
........\............\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG
........\............\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl
........\............\...\...\............\...................\Source-SynthesisOnly-AutoCompile
........\............\...\...\............\...................\Source-SynthesisOnly-AutoCompile_StrTbl
........\............\...\...\............\xreport\Gc_RvReportViewer-Current-Module
........\............\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
........\............\...\...\............\.......\Gc_RvReportViewer-Module-Data-even
........\............\...\...\............\.......\Gc_RvReportViewer-Module-Data-even_StrTbl
........\............\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
........\............\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
........\............\...\...\..REGISTRY__\Autonym\regkeys
........\............\...\...\............\bitgen\regkeys
........\............\...\...\............\...init\regkeys
........\............\...\...\............\common\regkeys
........\............\...\...\............\.pldfit\regkeys
........\............\...\...\............\dumpngdio\regkeys
........\............\...\...\............\ExpandedNetlistEngine\regkeys
........\............\...\...\............\fuse\regkeys
........\............\...\...\............\HierarchicalDesign\HDProject\regkeys
........\............\...\...\............\..................\regkeys
........\............\...\...\............\hprep6\regkeys
........\............\...\...\............\idem\regkeys
........\............\...\...\............\libgen\regkeys
........\............\...\...\............\map\regkeys
........\............\...\...\............\netgen\regkeys
........\............\...\...\............\.gc2edif\regkeys
........\............\...\...\............\...build\regkeys
........\............\...\...\............\..dbuild\regkeys
........\............\...\...\............\par\regkeys
........\............\...\...\............\.latgen\regkeys
........\............\...\...\............\ProjectNavigator\regkeys
........\............\...\...\............\................11\regkeys
........\............\...\...\............\................Gui\regkeys
........\............\...\...\............\runner\regk
........\auto_project_1.ipf
........\dcm.tfi
........\dcm.v
........\dcm_arwz.ucf
........\DCM_CORE.tfi
........\DCM_CORE.v
........\DCM_CORE_arwz.ucf
........\device_usage_statistics.html
........\edivider.gise
........\edivider.ise
........\edivider.ntrc_log
........\edivider.xise
........\........_xdb\cst.xbcd
........\............\tmp\ise\version
........\............\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
........\............\...\...\............\..................\.........\HDProject_StrTbl
........\............\...\...\............\..................\__stored_object_table__
........\............\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
........\............\...\...\............\.........\.......\RunOnce_tcl_StrTbl
........\............\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
........\............\...\...\............\................\................\dpm_project_main_StrTbl
........\............\...\...\............\................Gui\CSourceProcessView
........\............\...\...\............\...................\CSourceProcessView_StrTbl
........\............\...\...\............\...................\CViewSelector
........\............\...\...\............\...................\CViewSelector_StrTbl
........\............\...\...\............\...................\File-SynthesisOnly
........\............\...\...\............\...................\File-SynthesisOnly_StrTbl
........\............\...\...\............\...................\Library-SynthesisOnly
........\............\...\...\............\...................\Library-SynthesisOnly_StrTbl
........\............\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG
........\............\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl
........\............\...\...\............\...................\Source-SynthesisOnly-AutoCompile
........\............\...\...\............\...................\Source-SynthesisOnly-AutoCompile_StrTbl
........\............\...\...\............\xreport\Gc_RvReportViewer-Current-Module
........\............\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
........\............\...\...\............\.......\Gc_RvReportViewer-Module-Data-even
........\............\...\...\............\.......\Gc_RvReportViewer-Module-Data-even_StrTbl
........\............\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
........\............\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
........\............\...\...\..REGISTRY__\Autonym\regkeys
........\............\...\...\............\bitgen\regkeys
........\............\...\...\............\...init\regkeys
........\............\...\...\............\common\regkeys
........\............\...\...\............\.pldfit\regkeys
........\............\...\...\............\dumpngdio\regkeys
........\............\...\...\............\ExpandedNetlistEngine\regkeys
........\............\...\...\............\fuse\regkeys
........\............\...\...\............\HierarchicalDesign\HDProject\regkeys
........\............\...\...\............\..................\regkeys
........\............\...\...\............\hprep6\regkeys
........\............\...\...\............\idem\regkeys
........\............\...\...\............\libgen\regkeys
........\............\...\...\............\map\regkeys
........\............\...\...\............\netgen\regkeys
........\............\...\...\............\.gc2edif\regkeys
........\............\...\...\............\...build\regkeys
........\............\...\...\............\..dbuild\regkeys
........\............\...\...\............\par\regkeys
........\............\...\...\............\.latgen\regkeys
........\............\...\...\............\ProjectNavigator\regkeys
........\............\...\...\............\................11\regkeys
........\............\...\...\............\................Gui\regkeys
........\............\...\...\............\runner\regk