文件名称:ad7818_control
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本工程是使用Verilog语言，实现了对ad7818采样芯片的灵活控制，包含了原代码和Modelsim仿真程序和仿真结构图-Write by Verilog language.It s the controllor of the ad7818.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ad7818_control\ad_control.qpf
..............\ad_control.qsf
..............\ad_control.qws
..............\code\ad_control.v
..............\....\ad_control.v.bak
..............\....\tb_ad_control.v
..............\db\ad_control.db_info
..............\..\ad_control.eco.cdb
..............\..\ad_control.sld_design_entry.sci
..............\modelsim\ad_control\ad_control\verilog.asm
..............\........\..........\..........\_primary.dat
..............\........\..........\..........\_primary.vhd
..............\........\..........\tb_ad_control\verilog.asm
..............\........\..........\.............\_primary.dat
..............\........\..........\.............\_primary.vhd
..............\........\..........\_info
..............\........\ad_control.cr.mti
..............\........\ad_control.mpf
..............\........\vsim.wlf
..............\........\wave.do
..............\仿真时序\20120312201913.jpg
..............\....结果\20120312201913.jpg
..............\........\conv信号的时序.bmp
..............\........\全局仿真结果.bmp
..............\........\细节信号_001.bmp
..............\........\细节信号_002.bmp
..............\........\细节信号_003.bmp
..............\........\细节信号_004.bmp
..............\........\细节信号_005.bmp
..............\modelsim\ad_control\ad_control
..............\........\..........\tb_ad_control
..............\........\..........\_temp
..............\........\ad_control
..............\code
..............\db
..............\modelsim
..............\仿真时序
..............\仿真结果
ad7818_control
..............\ad_control.qsf
..............\ad_control.qws
..............\code\ad_control.v
..............\....\ad_control.v.bak
..............\....\tb_ad_control.v
..............\db\ad_control.db_info
..............\..\ad_control.eco.cdb
..............\..\ad_control.sld_design_entry.sci
..............\modelsim\ad_control\ad_control\verilog.asm
..............\........\..........\..........\_primary.dat
..............\........\..........\..........\_primary.vhd
..............\........\..........\tb_ad_control\verilog.asm
..............\........\..........\.............\_primary.dat
..............\........\..........\.............\_primary.vhd
..............\........\..........\_info
..............\........\ad_control.cr.mti
..............\........\ad_control.mpf
..............\........\vsim.wlf
..............\........\wave.do
..............\仿真时序\20120312201913.jpg
..............\....结果\20120312201913.jpg
..............\........\conv信号的时序.bmp
..............\........\全局仿真结果.bmp
..............\........\细节信号_001.bmp
..............\........\细节信号_002.bmp
..............\........\细节信号_003.bmp
..............\........\细节信号_004.bmp
..............\........\细节信号_005.bmp
..............\modelsim\ad_control\ad_control
..............\........\..........\tb_ad_control
..............\........\..........\_temp
..............\........\ad_control
..............\code
..............\db
..............\modelsim
..............\仿真时序
..............\仿真结果
ad7818_control