文件名称:verilog_sw_led
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采用verilog编写的FPGA程序，程序的功能是按键按键消抖，quartus II 开发。芯片型号是EP2C35F484C7，时钟50MHz。-FPGA verilog to write the program, the program function is the key button is debounced, quartus II development. The chip model is EP2C35F484C7, clock 50MHz
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下载文件列表
verilog_sw_led\db\prev_cmp_verilog_sw_led.asm.qmsg
..............\..\prev_cmp_verilog_sw_led.eda.qmsg
..............\..\prev_cmp_verilog_sw_led.fit.qmsg
..............\..\prev_cmp_verilog_sw_led.map.qmsg
..............\..\prev_cmp_verilog_sw_led.qmsg
..............\..\prev_cmp_verilog_sw_led.tan.qmsg
..............\..\verilog_sw_led.asm.qmsg
..............\..\verilog_sw_led.asm_labs.ddb
..............\..\verilog_sw_led.cbx.xml
..............\..\verilog_sw_led.cmp.bpm
..............\..\verilog_sw_led.cmp.cdb
..............\..\verilog_sw_led.cmp.ecobp
..............\..\verilog_sw_led.cmp.hdb
..............\..\verilog_sw_led.cmp.kpt
..............\..\verilog_sw_led.cmp.logdb
..............\..\verilog_sw_led.cmp.rdb
..............\..\verilog_sw_led.cmp.tdb
..............\..\verilog_sw_led.cmp0.ddb
..............\..\verilog_sw_led.cmp2.ddb
..............\..\verilog_sw_led.cmp_merge.kpt
..............\..\verilog_sw_led.db_info
..............\..\verilog_sw_led.eco.cdb
..............\..\verilog_sw_led.eda.qmsg
..............\..\verilog_sw_led.fit.qmsg
..............\..\verilog_sw_led.hier_info
..............\..\verilog_sw_led.hif
..............\..\verilog_sw_led.lpc.html
..............\..\verilog_sw_led.lpc.rdb
..............\..\verilog_sw_led.lpc.txt
..............\..\verilog_sw_led.map.bpm
..............\..\verilog_sw_led.map.cdb
..............\..\verilog_sw_led.map.ecobp
..............\..\verilog_sw_led.map.hdb
..............\..\verilog_sw_led.map.kpt
..............\..\verilog_sw_led.map.logdb
..............\..\verilog_sw_led.map.qmsg
..............\..\verilog_sw_led.map_bb.cdb
..............\..\verilog_sw_led.map_bb.hdb
..............\..\verilog_sw_led.map_bb.logdb
..............\..\verilog_sw_led.pre_map.cdb
..............\..\verilog_sw_led.pre_map.hdb
..............\..\verilog_sw_led.rtlv.hdb
..............\..\verilog_sw_led.rtlv_sg.cdb
..............\..\verilog_sw_led.rtlv_sg_swap.cdb
..............\..\verilog_sw_led.sgdiff.cdb
..............\..\verilog_sw_led.sgdiff.hdb
..............\..\verilog_sw_led.sld_design_entry.sci
..............\..\verilog_sw_led.sld_design_entry_dsc.sci
..............\..\verilog_sw_led.syn_hier_info
..............\..\verilog_sw_led.tan.qmsg
..............\..\verilog_sw_led.tis_db_list.ddb
..............\..\verilog_sw_led.tmw_info
..............\..\wed.wsf
..............\incremental_db\compiled_partitions\verilog_sw_led.root_partition.cmp.atm
..............\..............\...................\verilog_sw_led.root_partition.cmp.dfp
..............\..............\...................\verilog_sw_led.root_partition.cmp.hdbx
..............\..............\...................\verilog_sw_led.root_partition.cmp.kpt
..............\..............\...................\verilog_sw_led.root_partition.cmp.logdb
..............\..............\...................\verilog_sw_led.root_partition.cmp.rcf
..............\..............\...................\verilog_sw_led.root_partition.map.atm
..............\..............\...................\verilog_sw_led.root_partition.map.dpi
..............\..............\...................\verilog_sw_led.root_partition.map.hdbx
..............\..............\...................\verilog_sw_led.root_partition.map.kpt
..............\..............\README
..............\simulation\modelsim\modelsim.ini
..............\..........\........\msim_transcript
..............\..........\........\rtl_work\verilog_sw_led\verilog.prw
..............\..........\........\........\..............\verilog.psm
..............\..........\........\........\..............\_primary.dat
..............\..........\........\........\..............\_primary.dbs
..............\..........\........\........\..............\_primary.vhd
..............\..........\........\........\.............._vlg_tst\verilog.prw
..............\..........\........\........\......................\verilog.psm
..............\..........\........\........\......................\_primary.dat
..............\..........\........\........\......................\_primary.dbs
..............\..........\........\........\......................\_primary.v
..............\..\prev_cmp_verilog_sw_led.eda.qmsg
..............\..\prev_cmp_verilog_sw_led.fit.qmsg
..............\..\prev_cmp_verilog_sw_led.map.qmsg
..............\..\prev_cmp_verilog_sw_led.qmsg
..............\..\prev_cmp_verilog_sw_led.tan.qmsg
..............\..\verilog_sw_led.asm.qmsg
..............\..\verilog_sw_led.asm_labs.ddb
..............\..\verilog_sw_led.cbx.xml
..............\..\verilog_sw_led.cmp.bpm
..............\..\verilog_sw_led.cmp.cdb
..............\..\verilog_sw_led.cmp.ecobp
..............\..\verilog_sw_led.cmp.hdb
..............\..\verilog_sw_led.cmp.kpt
..............\..\verilog_sw_led.cmp.logdb
..............\..\verilog_sw_led.cmp.rdb
..............\..\verilog_sw_led.cmp.tdb
..............\..\verilog_sw_led.cmp0.ddb
..............\..\verilog_sw_led.cmp2.ddb
..............\..\verilog_sw_led.cmp_merge.kpt
..............\..\verilog_sw_led.db_info
..............\..\verilog_sw_led.eco.cdb
..............\..\verilog_sw_led.eda.qmsg
..............\..\verilog_sw_led.fit.qmsg
..............\..\verilog_sw_led.hier_info
..............\..\verilog_sw_led.hif
..............\..\verilog_sw_led.lpc.html
..............\..\verilog_sw_led.lpc.rdb
..............\..\verilog_sw_led.lpc.txt
..............\..\verilog_sw_led.map.bpm
..............\..\verilog_sw_led.map.cdb
..............\..\verilog_sw_led.map.ecobp
..............\..\verilog_sw_led.map.hdb
..............\..\verilog_sw_led.map.kpt
..............\..\verilog_sw_led.map.logdb
..............\..\verilog_sw_led.map.qmsg
..............\..\verilog_sw_led.map_bb.cdb
..............\..\verilog_sw_led.map_bb.hdb
..............\..\verilog_sw_led.map_bb.logdb
..............\..\verilog_sw_led.pre_map.cdb
..............\..\verilog_sw_led.pre_map.hdb
..............\..\verilog_sw_led.rtlv.hdb
..............\..\verilog_sw_led.rtlv_sg.cdb
..............\..\verilog_sw_led.rtlv_sg_swap.cdb
..............\..\verilog_sw_led.sgdiff.cdb
..............\..\verilog_sw_led.sgdiff.hdb
..............\..\verilog_sw_led.sld_design_entry.sci
..............\..\verilog_sw_led.sld_design_entry_dsc.sci
..............\..\verilog_sw_led.syn_hier_info
..............\..\verilog_sw_led.tan.qmsg
..............\..\verilog_sw_led.tis_db_list.ddb
..............\..\verilog_sw_led.tmw_info
..............\..\wed.wsf
..............\incremental_db\compiled_partitions\verilog_sw_led.root_partition.cmp.atm
..............\..............\...................\verilog_sw_led.root_partition.cmp.dfp
..............\..............\...................\verilog_sw_led.root_partition.cmp.hdbx
..............\..............\...................\verilog_sw_led.root_partition.cmp.kpt
..............\..............\...................\verilog_sw_led.root_partition.cmp.logdb
..............\..............\...................\verilog_sw_led.root_partition.cmp.rcf
..............\..............\...................\verilog_sw_led.root_partition.map.atm
..............\..............\...................\verilog_sw_led.root_partition.map.dpi
..............\..............\...................\verilog_sw_led.root_partition.map.hdbx
..............\..............\...................\verilog_sw_led.root_partition.map.kpt
..............\..............\README
..............\simulation\modelsim\modelsim.ini
..............\..........\........\msim_transcript
..............\..........\........\rtl_work\verilog_sw_led\verilog.prw
..............\..........\........\........\..............\verilog.psm
..............\..........\........\........\..............\_primary.dat
..............\..........\........\........\..............\_primary.dbs
..............\..........\........\........\..............\_primary.vhd
..............\..........\........\........\.............._vlg_tst\verilog.prw
..............\..........\........\........\......................\verilog.psm
..............\..........\........\........\......................\_primary.dat
..............\..........\........\........\......................\_primary.dbs
..............\..........\........\........\......................\_primary.v