文件名称:can_controller

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1015kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • w*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

CAN protocol controller实例,总体构架,模块实现,模块测试-CAN protocol controller examples, and the overall structure, modules realize, module testing
(系统自动生成,下载前可以参看下载内容)

下载文件列表

can_controller

..............\can_acf.v

..............\can_bsp.v

..............\can_btl.v

..............\can_controller.cr.mti

..............\can_controller.mpf

..............\can_crc.v

..............\can_defines.v

..............\can_fifo.v

..............\can_ibo.v

..............\can_register.v

..............\can_registers.v

..............\can_register_asyn.v

..............\can_register_asyn_syn.v

..............\can_register_syn.v

..............\can_testbench.v

..............\can_testbench_defines.v

..............\can_top.v

..............\chart

..............\.....\Thumbs.db

..............\.....\图8-10.bmp

..............\.....\图8-11.bmp

..............\.....\图8-12.bmp

..............\.....\图8-14.bmp

..............\.....\图8-15.bmp

..............\.....\图8-16.bmp

..............\.....\图8-17.bmp

..............\.....\图8-20.bmp

..............\.....\图8-21.bmp

..............\.....\图8-22.bmp

..............\.....\图8-5.bmp

..............\.....\图8-8.bmp

..............\timescale.v

..............\transcript

..............\vsim.wlf

..............\wave

..............\....\can_acf.bmp

..............\....\can_bsp.bmp

..............\....\can_btl.bmp

..............\....\can_crc.bmp

..............\....\can_fifo.bmp

..............\....\can_testbench.bmp

..............\....\can_top.bmp

..............\work

..............\....\can_acf

..............\....\.......\verilog.asm

..............\....\.......\_primary.dat

..............\....\.......\_primary.vhd

..............\....\can_bsp

..............\....\.......\verilog.asm

..............\....\.......\_primary.dat

..............\....\.......\_primary.vhd

..............\....\can_btl

..............\....\.......\verilog.asm

..............\....\.......\_primary.dat

..............\....\.......\_primary.vhd

..............\....\can_crc

..............\....\.......\verilog.asm

..............\....\.......\_primary.dat

..............\....\.......\_primary.vhd

..............\....\can_fifo

..............\....\........\verilog.asm

..............\....\........\_primary.dat

..............\....\........\_primary.vhd

..............\....\can_ibo

..............\....\.......\verilog.asm

..............\....\.......\_primary.dat

..............\....\.......\_primary.vhd

..............\....\can_register

..............\....\can_registers

..............\....\.............\verilog.asm

..............\....\.............\_primary.dat

..............\....\.............\_primary.vhd

..............\....\............\verilog.asm

..............\....\............\_primary.dat

..............\....\............\_primary.vhd

..............\....\can_register_asyn

..............\....\.................\verilog.asm

..............\....\.................\_primary.dat

..............\....\.................\_primary.vhd

..............\....\can_register_asyn_syn

..............\....\.....................\verilog.asm

..............\....\.....................\_primary.dat

..............\....\.....................\_primary.vhd

..............\....\can_register_syn

..............\....\................\verilog.asm

..............\....\................\_primary.dat

..............\....\................\_primary.vhd

..............\....\can_testbench

..............\....\.............\verilog.asm

..............\....\.............\_primary.dat

..............\....\.............\_primary.vhd

..............\....\can_top

..............\....\.......\verilog.asm

..............\....\.......\_primary.dat

..............\....\.......\_primary.vhd

..............\....\_info

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