文件名称:calender
介绍说明－－下载内容均来自于网络，请自行研究使用
这是用Verilog语言编写的万年历源代码，其中以小时为最小单位，可以区分闰年。有瑕疵还望海涵。-This is the calendar source code written in Verilog language, which hour is the smallest unit that can differentiate between leap years.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
calender\calender.v
........\calender.v.bak
........\calender_test.v
........\calender_test.v.bak
........\day.v
........\day.v.bak
........\day_con.v
........\day_con.v.bak
........\hour.v
........\hour.v.bak
........\month.v
........\month.v.bak
........\week.v
........\week.v.bak
........\.ork\calender\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\........_test\verilog.asm
........\....\.............\_primary.dat
........\....\.............\_primary.vhd
........\....\day\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\..._con\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\hour\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\month\verilog.asm
........\....\.....\_primary.dat
........\....\.....\_primary.vhd
........\....\week\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\year\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\...._con\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\_info
........\year.v
........\year.v.bak
........\year_con.v
........\year_con.v.bak
........\work\calender
........\....\calender_test
........\....\day
........\....\day_con
........\....\hour
........\....\month
........\....\week
........\....\year
........\....\year_con
........\work
calender
........\calender.v.bak
........\calender_test.v
........\calender_test.v.bak
........\day.v
........\day.v.bak
........\day_con.v
........\day_con.v.bak
........\hour.v
........\hour.v.bak
........\month.v
........\month.v.bak
........\week.v
........\week.v.bak
........\.ork\calender\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\........_test\verilog.asm
........\....\.............\_primary.dat
........\....\.............\_primary.vhd
........\....\day\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\..._con\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\hour\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\month\verilog.asm
........\....\.....\_primary.dat
........\....\.....\_primary.vhd
........\....\week\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\year\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\...._con\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\_info
........\year.v
........\year.v.bak
........\year_con.v
........\year_con.v.bak
........\work\calender
........\....\calender_test
........\....\day
........\....\day_con
........\....\hour
........\....\month
........\....\week
........\....\year
........\....\year_con
........\work
calender