文件名称:comp
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verilog FPGA060 比较器实验例程和文档-verilog FPGA060 comparator test routines and documentation
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下载文件列表
comp\comp.prj
....\designer\impl1\comp.adb
....\........\.....\comp.dat
....\........\.....\......tf\verify.log
....\........\.....\comp.ide_des
....\........\.....\comp.tcl
....\........\.....\designer.log
....\hdl\comp.v
....\simulation\modelsim.ini
....\.martgen\smartgen.aws
....\.ynthesis\.recordref
....\.........\comp.areasrr
....\.........\comp.edn
....\.........\comp.map
....\.........\comp.pdc
....\.........\comp.sdf
....\.........\comp.so
....\.........\comp.srd
....\.........\comp.srm
....\.........\comp.srr
....\.........\comp.srs
....\.........\comp.szr
....\.........\comp.tlg
....\.........\comp_sdc.sdc
....\.........\comp_syn.prj
....\.........\run_options.txt
....\.........\stdout.log
....\.........\.yntmp\comp.plg
....\.........\traplog.tlg
....\viewdraw\vf\project.lst
....\........\viewdraw.ini
....\designer\impl1\comp.dtf
....\........\.....\simulation
....\........\impl1
....\synthesis\backup
....\.........\coreip
....\.........\syntmp
....\viewdraw\sch
....\........\sym
....\........\vf
....\........\wir
....\component
....\constraint
....\coreconsole
....\designer
....\hdl
....\phy_synthesis
....\simulation
....\smartgen
....\stimulus
....\synthesis
....\viewdraw
comp
....\designer\impl1\comp.adb
....\........\.....\comp.dat
....\........\.....\......tf\verify.log
....\........\.....\comp.ide_des
....\........\.....\comp.tcl
....\........\.....\designer.log
....\hdl\comp.v
....\simulation\modelsim.ini
....\.martgen\smartgen.aws
....\.ynthesis\.recordref
....\.........\comp.areasrr
....\.........\comp.edn
....\.........\comp.map
....\.........\comp.pdc
....\.........\comp.sdf
....\.........\comp.so
....\.........\comp.srd
....\.........\comp.srm
....\.........\comp.srr
....\.........\comp.srs
....\.........\comp.szr
....\.........\comp.tlg
....\.........\comp_sdc.sdc
....\.........\comp_syn.prj
....\.........\run_options.txt
....\.........\stdout.log
....\.........\.yntmp\comp.plg
....\.........\traplog.tlg
....\viewdraw\vf\project.lst
....\........\viewdraw.ini
....\designer\impl1\comp.dtf
....\........\.....\simulation
....\........\impl1
....\synthesis\backup
....\.........\coreip
....\.........\syntmp
....\viewdraw\sch
....\........\sym
....\........\vf
....\........\wir
....\component
....\constraint
....\coreconsole
....\designer
....\hdl
....\phy_synthesis
....\simulation
....\smartgen
....\stimulus
....\synthesis
....\viewdraw
comp