文件名称:booth_multiplier

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [Windows] [程序]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 10.96mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • K***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

This source code makes 8 X 8 booth multiplier and it is coded in Velilog HDL.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

berwer\.simvision\dbrowser-bookmarks

......\..........\schematic-bookmarks

......\..........\source-bookmarks

......\INCA_libs\worklib\.cdsvmod

......\.........\.......\.inca.db.165.sun4v

......\.........\.......\inca.sun4v.165.pak

......\hdl\TB_Booth_Mul_8x8.v

......\...\booth_multiplier.v

......\waves.shm\waves-1.trn

......\.........\waves-2.trn

......\.........\waves.dsn

......\.........\waves.trn

......\.nclaunch.dd

......\booth_2009307045_RCA.dsn

......\booth_2009307045_RCA.trn

......\cds.lib

......\hdl.var

......\ncelab.log

......\nclaunch.key

......\ncsim.key

......\ncsim.log

......\ncvlog.log

......\out.dat

......2\hdl\TB_Booth_Mul_8x8.v

.......\...\TB_Booth_Mul_8x8.v~

.......\...\booth_multiplier.v

.......\...\booth_multiplier.v~

.......\lib\work\ADDER_TREE.mr

.......\...\....\BOOTH_2009307045.mr

.......\...\....\CARRY_LA_GEN.mr

.......\...\....\COMPRESSOR4_2.mr

.......\...\....\Carry_LA_Gen-verilog-verilog.syn

.......\...\....\Carry_LA_Gen-verilog.pvl

.......\...\....\Carry_LA_Gen-verilog.syn

.......\...\....\FULL_ADDER.mr

.......\...\....\HALF_ADDER.mr

.......\...\....\INPUT_BUFFER.mr

.......\...\....\LOOKAHEAD.mr

.......\...\....\LOOKAHEAD_4.mr

.......\...\....\LOOKAHEAD_4_MSB.mr

.......\...\....\PARTIAL_PRODUCT_GENERATOR.mr

.......\...\....\adder_tree-verilog-verilog.syn

.......\...\....\adder_tree-verilog.pvl

.......\...\....\adder_tree-verilog.syn

.......\...\....\booth_2009307045-verilog-verilog.syn

.......\...\....\booth_2009307045-verilog.pvl

.......\...\....\booth_2009307045-verilog.syn

.......\...\....\compressor4_2-verilog-verilog.syn

.......\...\....\compressor4_2-verilog.pvl

.......\...\....\compressor4_2-verilog.syn

.......\...\....\full_adder-verilog-verilog.syn

.......\...\....\full_adder-verilog.pvl

.......\...\....\full_adder-verilog.syn

.......\...\....\half_adder-verilog-verilog.syn

.......\...\....\half_adder-verilog.pvl

.......\...\....\half_adder-verilog.syn

.......\...\....\input_buffer-verilog-verilog.syn

.......\...\....\input_buffer-verilog.pvl

.......\...\....\input_buffer-verilog.syn

.......\...\....\lookahead-verilog-verilog.syn

.......\...\....\lookahead-verilog.pvl

.......\...\....\lookahead-verilog.syn

.......\...\....\lookahead_4-verilog-verilog.syn

.......\...\....\lookahead_4-verilog.pvl

.......\...\....\lookahead_4-verilog.syn

.......\...\....\lookahead_4_msb-verilog-verilog.syn

.......\...\....\lookahead_4_msb-verilog.pvl

.......\...\....\lookahead_4_msb-verilog.syn

.......\...\....\partial_product_generator-verilog-verilog.syn

.......\...\....\partial_product_generator-verilog.pvl

.......\...\....\partial_product_generator-verilog.syn

.......\...\ci025a.sdb

.......\...\ci025a_02.db

.......\.og\command.log

.......\...\filename.log

.......\mapped

.......\netlist

.......\report

.......\script\booth_read.scr

.......\......\booth_read.scr~

.......\......\booth_syn.scr

.......\......\booth_syn.scr~

.......\sdc

.......\unmapped

.......\.synopsys_dc.setup

.ooth\.simvision\dbrowser-bookmarks

.....\..........\schematic-bookmarks

.....\..........\source-bookmarks

.....\INCA_libs\worklib\.cdsvmod

.....\.........\.......\.inca.db.165.sun4v

.....\.........\.......\inca.sun4v.165.pak

.....\hdl\TB_Booth_Mul_8x8.v

.....\...\booth_multiplier.v

.....\...\booth_multiplier.v~

.....\lib\work\ADDER_TREE.mr

.....\...\....\BOOTH_2009307045.mr

.....\...\....\CARRY_LA_GEN.mr

.....\...\....\COMPRESSOR4_2.mr

.....\...\....\Carry_LA_Gen-verilog-verilog.syn

.....\...\....\Carry_LA_Gen-verilog.pvl

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