文件名称:verilog_example
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集成了多个集成电路设计源代码，保证测试正确完整-verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
verilog_example
...............\BUS_ARBITRATOR1.v
...............\BUS_ARBITRATOR1_testbench.v
...............\BUS_ARBITRATOR2.v
...............\CNT_LFSR_DIV13.v
...............\CNT_LFSR_DIV13_t.v
...............\CNT_LFSR_DIV31.v
...............\FSM_1.v
...............\FSM_1_BAD.v
...............\Fsm_example1.v
...............\Fsm_example1_3.v
...............\Fsm_example1_4.v
...............\Fsm_example4.v
...............\Fsm_example4_test.v
...............\LFSR_8bit.v
...............\LFSR_8bit_256.v
...............\LFSR_8bit_test.v
...............\LFSR_GENERiC_MOD.v
...............\SRF_arbitrator.v
...............\Shifter_4bit.v
...............\add_4_r_test.v
...............\arbitrator_prj.cr.mti
...............\arbitrator_prj.mpf
...............\asyn_rst_syn_release.v
...............\carry.v
...............\carryAbbrev.v
...............\carryX.v
...............\clk_3div.v
...............\clk_3div_tb.v
...............\clk_div_phase.v
...............\clk_div_phase_tb.v
...............\counter4.v
...............\counter4.v.bak
...............\data_process.data
...............\data_process.v
...............\data_process.v.bak
...............\data_process_testbench.v
...............\data_process_testbench.v.bak
...............\display_cmds.v
...............\down_counter.v
...............\example.v
...............\fifo.cr.mti
...............\fifo.mpf
...............\fifo_buffer.v
...............\fifo_buffer.v.bak
...............\fifo_buffer_testbench.v
...............\fifo_buffer_testbench.v.bak
...............\file_operation.v
...............\file_operation.v.bak
...............\fulladd_2bit.v
...............\fulladd_2bit_test.v
...............\fulladder_16bit
...............\fulladder_16bit.v
...............\include_example.v
...............\include_example.v.bak
...............\module_example.v
...............\module_example.v.bak
...............\monitor_use.v
...............\muti_delay.v
...............\muti_delay.v.bak
...............\one_notsohot.v
...............\sell_out.v
...............\shift.v
...............\shift_reg.v
...............\state1.v
...............\state2.v
...............\state2_default.v
...............\state3.v
...............\strobe_use.v
...............\sync_counter_10.v
...............\test.txt
...............\test_time.v
...............\test_time.v.bak
...............\testfixture_down_counter.v
...............\traffic_lights.bmp
...............\traffic_lights.v
...............\vish_stacktrace.vstf
...............\vsim.wlf
...............\work
...............\....\_info
...............\....\fifo_buffer
...............\....\...........\_primary.dat
...............\....\...........\_primary.vhd
...............\....\...........\verilog.asm
...............\....\fifo_buffer_testbench
...............\....\.....................\_primary.dat
...............\....\.....................\_primary.vhd
...............\....\.....................\verilog.asm
...............\....\module_example
...............\....\..............\_primary.dat
...............\....\..............\_primary.vhd
...............\....\..............\verilog.asm
...............\writetofile.v
...............\BUS_ARBITRATOR1.v
...............\BUS_ARBITRATOR1_testbench.v
...............\BUS_ARBITRATOR2.v
...............\CNT_LFSR_DIV13.v
...............\CNT_LFSR_DIV13_t.v
...............\CNT_LFSR_DIV31.v
...............\FSM_1.v
...............\FSM_1_BAD.v
...............\Fsm_example1.v
...............\Fsm_example1_3.v
...............\Fsm_example1_4.v
...............\Fsm_example4.v
...............\Fsm_example4_test.v
...............\LFSR_8bit.v
...............\LFSR_8bit_256.v
...............\LFSR_8bit_test.v
...............\LFSR_GENERiC_MOD.v
...............\SRF_arbitrator.v
...............\Shifter_4bit.v
...............\add_4_r_test.v
...............\arbitrator_prj.cr.mti
...............\arbitrator_prj.mpf
...............\asyn_rst_syn_release.v
...............\carry.v
...............\carryAbbrev.v
...............\carryX.v
...............\clk_3div.v
...............\clk_3div_tb.v
...............\clk_div_phase.v
...............\clk_div_phase_tb.v
...............\counter4.v
...............\counter4.v.bak
...............\data_process.data
...............\data_process.v
...............\data_process.v.bak
...............\data_process_testbench.v
...............\data_process_testbench.v.bak
...............\display_cmds.v
...............\down_counter.v
...............\example.v
...............\fifo.cr.mti
...............\fifo.mpf
...............\fifo_buffer.v
...............\fifo_buffer.v.bak
...............\fifo_buffer_testbench.v
...............\fifo_buffer_testbench.v.bak
...............\file_operation.v
...............\file_operation.v.bak
...............\fulladd_2bit.v
...............\fulladd_2bit_test.v
...............\fulladder_16bit
...............\fulladder_16bit.v
...............\include_example.v
...............\include_example.v.bak
...............\module_example.v
...............\module_example.v.bak
...............\monitor_use.v
...............\muti_delay.v
...............\muti_delay.v.bak
...............\one_notsohot.v
...............\sell_out.v
...............\shift.v
...............\shift_reg.v
...............\state1.v
...............\state2.v
...............\state2_default.v
...............\state3.v
...............\strobe_use.v
...............\sync_counter_10.v
...............\test.txt
...............\test_time.v
...............\test_time.v.bak
...............\testfixture_down_counter.v
...............\traffic_lights.bmp
...............\traffic_lights.v
...............\vish_stacktrace.vstf
...............\vsim.wlf
...............\work
...............\....\_info
...............\....\fifo_buffer
...............\....\...........\_primary.dat
...............\....\...........\_primary.vhd
...............\....\...........\verilog.asm
...............\....\fifo_buffer_testbench
...............\....\.....................\_primary.dat
...............\....\.....................\_primary.vhd
...............\....\.....................\verilog.asm
...............\....\module_example
...............\....\..............\_primary.dat
...............\....\..............\_primary.vhd
...............\....\..............\verilog.asm
...............\writetofile.v