文件名称:test
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一个进位计数器的简单verlag实现，仿真无误-A simple binary counter verlag achieved, the simulation is correct ... ...
(系统自动生成,下载前可以参看下载内容)
下载文件列表
test\modelsim.ini
....\tb_carry_counter.v
....\tb_carry_counter.v.bak
....\trigger_carry_counter.v
....\trigger_carry_counter.v.bak
....\vsim.wlf
....\work\@d_@f@f\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\.t_@f@f\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\ripple_carry_counter\verilog.asm
....\....\....................\_primary.dat
....\....\....................\_primary.vhd
....\....\stimulus\verilog.asm
....\....\........\_primary.dat
....\....\........\_primary.vhd
....\....\_info
....\....\@d_@f@f
....\....\@t_@f@f
....\....\ripple_carry_counter
....\....\stimulus
....\work
test
....\tb_carry_counter.v
....\tb_carry_counter.v.bak
....\trigger_carry_counter.v
....\trigger_carry_counter.v.bak
....\vsim.wlf
....\work\@d_@f@f\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\.t_@f@f\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\ripple_carry_counter\verilog.asm
....\....\....................\_primary.dat
....\....\....................\_primary.vhd
....\....\stimulus\verilog.asm
....\....\........\_primary.dat
....\....\........\_primary.vhd
....\....\_info
....\....\@d_@f@f
....\....\@t_@f@f
....\....\ripple_carry_counter
....\....\stimulus
....\work
test