文件名称:Computer-Architecture-lab3
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计算机组成实验作业3，fpga开发板，verilog语言编写-Composition of experimental computer operating 3, fpga development board, verilog language
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09级计组实验_B班_31组_5090309744_谢聪_实验3代码\ALU.v
...............................................\aluctr.v
...............................................\aluctr_guide.ncd
...............................................\aluctr_prev_built.ngd
...............................................\aluctr_summary.html
...............................................\ALU_guide.ncd
...............................................\ALU_summary.html
...............................................\ctr.v
...............................................\ctr_guide.ncd
...............................................\ctr_isim_beh.wdb
...............................................\ctr_prev_built.ngd
...............................................\ctr_summary.html
...............................................\lab3.gise
...............................................\lab3.ise
...............................................\lab3.xise
...............................................\...._xdb\tmp\ise\version
...............................................\........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
...............................................\........\...\...\............\..................\.........\HDProject_StrTbl
...............................................\........\...\...\............\..................\__stored_object_table__
...............................................\........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
...............................................\........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
...............................................\........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
...............................................\........\...\...\............\................\................\dpm_project_main_StrTbl
...............................................\........\...\...\............\................Gui\CViewSelector
...............................................\........\...\...\............\...................\CViewSelector_StrTbl
...............................................\........\...\...\............\...................\File-SynthesisOnly
...............................................\........\...\...\............\...................\File-SynthesisOnly_StrTbl
...............................................\........\...\...\............\...................\Library-SynthesisOnly
...............................................\........\...\...\............\...................\Library-SynthesisOnly_StrTbl
...............................................\........\...\...\............\...................\Process-BehavioralSim-
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl
...............................................\........\...\...\............\...................\Process-BehavioralSim-_StrTbl
...............................................\........\...\...\............\...................\Process-PostRouteSim-
...............................................\........\...\...\............\...................\Process-PostRouteSim-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-PostRouteSim-DESUT_VERILOG_StrTbl
...............................................\........\...\...\............\...................\Process-PostRouteSim-_StrTbl
...............................................\........\...\...\............\...................\Process-SynthesisOnly-
...............................................\........\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl
...............................................\........\...\...\............\.........
...............................................\aluctr.v
...............................................\aluctr_guide.ncd
...............................................\aluctr_prev_built.ngd
...............................................\aluctr_summary.html
...............................................\ALU_guide.ncd
...............................................\ALU_summary.html
...............................................\ctr.v
...............................................\ctr_guide.ncd
...............................................\ctr_isim_beh.wdb
...............................................\ctr_prev_built.ngd
...............................................\ctr_summary.html
...............................................\lab3.gise
...............................................\lab3.ise
...............................................\lab3.xise
...............................................\...._xdb\tmp\ise\version
...............................................\........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
...............................................\........\...\...\............\..................\.........\HDProject_StrTbl
...............................................\........\...\...\............\..................\__stored_object_table__
...............................................\........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
...............................................\........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
...............................................\........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
...............................................\........\...\...\............\................\................\dpm_project_main_StrTbl
...............................................\........\...\...\............\................Gui\CViewSelector
...............................................\........\...\...\............\...................\CViewSelector_StrTbl
...............................................\........\...\...\............\...................\File-SynthesisOnly
...............................................\........\...\...\............\...................\File-SynthesisOnly_StrTbl
...............................................\........\...\...\............\...................\Library-SynthesisOnly
...............................................\........\...\...\............\...................\Library-SynthesisOnly_StrTbl
...............................................\........\...\...\............\...................\Process-BehavioralSim-
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl
...............................................\........\...\...\............\...................\Process-BehavioralSim-_StrTbl
...............................................\........\...\...\............\...................\Process-PostRouteSim-
...............................................\........\...\...\............\...................\Process-PostRouteSim-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-PostRouteSim-DESUT_VERILOG_StrTbl
...............................................\........\...\...\............\...................\Process-PostRouteSim-_StrTbl
...............................................\........\...\...\............\...................\Process-SynthesisOnly-
...............................................\........\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl
...............................................\........\...\...\............\.........