文件名称:uart
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 197kb
- 下载次数：
- 0次
- 提 供 者：
- renya*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
用verilog编写的uart代码，比较适合初学者练练手，包含初始化，收发等模块-Written code with verilog uart, more suitable for beginners practice your hand, including initialization, sending and receiving modules
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart\bd\my_uart_top.asm.qmsg
....\..\my_uart_top.cbx.xml
....\..\my_uart_top.cmp.bpm
....\..\my_uart_top.cmp.cdb
....\..\my_uart_top.cmp.ecobp
....\..\my_uart_top.cmp.hdb
....\..\my_uart_top.cmp.kpt
....\..\my_uart_top.cmp.logdb
....\..\my_uart_top.cmp.rdb
....\..\my_uart_top.cmp.tdb
....\..\my_uart_top.cmp0.ddb
....\..\my_uart_top.cmp_merge.kpt
....\..\my_uart_top.db_info
....\..\my_uart_top.eco.cdb
....\..\my_uart_top.fit.qmsg
....\..\my_uart_top.hier_info
....\..\my_uart_top.hif
....\..\my_uart_top.lpc.html
....\..\my_uart_top.lpc.rdb
....\..\my_uart_top.lpc.txt
....\..\my_uart_top.map.bpm
....\..\my_uart_top.map.cdb
....\..\my_uart_top.map.ecobp
....\..\my_uart_top.map.hdb
....\..\my_uart_top.map.kpt
....\..\my_uart_top.map.logdb
....\..\my_uart_top.map.qmsg
....\..\my_uart_top.map_bb.cdb
....\..\my_uart_top.map_bb.hdb
....\..\my_uart_top.map_bb.logdb
....\..\my_uart_top.pre_map.cdb
....\..\my_uart_top.pre_map.hdb
....\..\my_uart_top.rtlv.hdb
....\..\my_uart_top.rtlv_sg.cdb
....\..\my_uart_top.rtlv_sg_swap.cdb
....\..\my_uart_top.sgdiff.cdb
....\..\my_uart_top.sgdiff.hdb
....\..\my_uart_top.sld_design_entry.sci
....\..\my_uart_top.sld_design_entry_dsc.sci
....\..\my_uart_top.syn_hier_info
....\..\my_uart_top.tan.qmsg
....\..\my_uart_top.tis_db_list.ddb
....\..\my_uart_top.tmw_info
....\incremental\compiled_partitions\my_uart_top.root_partition.cmp.atm
....\...........\...................\my_uart_top.root_partition.cmp.dfp
....\...........\...................\my_uart_top.root_partition.cmp.hdbx
....\...........\...................\my_uart_top.root_partition.cmp.kpt
....\...........\...................\my_uart_top.root_partition.cmp.logdb
....\...........\...................\my_uart_top.root_partition.cmp.rcf
....\...........\...................\my_uart_top.root_partition.map.atm
....\...........\...................\my_uart_top.root_partition.map.dpi
....\...........\...................\my_uart_top.root_partition.map.hdbx
....\...........\...................\my_uart_top.root_partition.map.kpt
....\...........\README
....\simulation\modelsim\modelsim.ini
....\..........\........\msim_transcript
....\..........\........\my_uart_top_run_msim_rtl_verilog.do
....\..........\........\my_uart_top_run_msim_rtl_verilog.do.bak
....\..........\........\rtl_work\my_uart_rx\verilog.psm
....\..........\........\........\..........\_primary.dat
....\..........\........\........\..........\_primary.dbs
....\..........\........\........\..........\_primary.vhd
....\..........\........\........\........top\verilog.psm
....\..........\........\........\...........\_primary.dat
....\..........\........\........\...........\_primary.dbs
....\..........\........\........\...........\_primary.vhd
....\..........\........\........\.........x\verilog.psm
....\..........\........\........\..........\_primary.dat
....\..........\........\........\..........\_primary.dbs
....\..........\........\........\..........\_primary.vhd
....\..........\........\........\speed_select\verilog.psm
....\..........\........\........\............\_primary.dat
....\..........\........\........\............\_primary.dbs
....\..........\........\........\............\_primary.vhd
....\..........\........\........\_info
....\..........\........\........\_vmake
....\speedselect.v
....\uart_rx.v
....\uart_top.asm.rpt
....\uart_top.done
....\uart_top.fit.rpt
....\uart_top.fit.summary
....\uart_top.flow.rpt
....\uart_top.map.rpt
....\uart_top.map.summary
....\uart_top.pin
....\uart_top.pof
....\uart_top.qpf
....\uart_top.qsf
....\uart_top.qws
....\uart_top.sof
....\uart_top.tan.rpt
....\uart_top.v
....\uart_top_nativelink_simulation.rpt
....\uart_tx.v
....\simulation\modelsim\rtl_work\my_uart_rx
....\..........\........\........\my_uart_top
....\..........\........\........\my_uart_tx
....\..........\........\........\speed_select
....\..........\........\........\_temp
....\..\my_uart_top.cbx.xml
....\..\my_uart_top.cmp.bpm
....\..\my_uart_top.cmp.cdb
....\..\my_uart_top.cmp.ecobp
....\..\my_uart_top.cmp.hdb
....\..\my_uart_top.cmp.kpt
....\..\my_uart_top.cmp.logdb
....\..\my_uart_top.cmp.rdb
....\..\my_uart_top.cmp.tdb
....\..\my_uart_top.cmp0.ddb
....\..\my_uart_top.cmp_merge.kpt
....\..\my_uart_top.db_info
....\..\my_uart_top.eco.cdb
....\..\my_uart_top.fit.qmsg
....\..\my_uart_top.hier_info
....\..\my_uart_top.hif
....\..\my_uart_top.lpc.html
....\..\my_uart_top.lpc.rdb
....\..\my_uart_top.lpc.txt
....\..\my_uart_top.map.bpm
....\..\my_uart_top.map.cdb
....\..\my_uart_top.map.ecobp
....\..\my_uart_top.map.hdb
....\..\my_uart_top.map.kpt
....\..\my_uart_top.map.logdb
....\..\my_uart_top.map.qmsg
....\..\my_uart_top.map_bb.cdb
....\..\my_uart_top.map_bb.hdb
....\..\my_uart_top.map_bb.logdb
....\..\my_uart_top.pre_map.cdb
....\..\my_uart_top.pre_map.hdb
....\..\my_uart_top.rtlv.hdb
....\..\my_uart_top.rtlv_sg.cdb
....\..\my_uart_top.rtlv_sg_swap.cdb
....\..\my_uart_top.sgdiff.cdb
....\..\my_uart_top.sgdiff.hdb
....\..\my_uart_top.sld_design_entry.sci
....\..\my_uart_top.sld_design_entry_dsc.sci
....\..\my_uart_top.syn_hier_info
....\..\my_uart_top.tan.qmsg
....\..\my_uart_top.tis_db_list.ddb
....\..\my_uart_top.tmw_info
....\incremental\compiled_partitions\my_uart_top.root_partition.cmp.atm
....\...........\...................\my_uart_top.root_partition.cmp.dfp
....\...........\...................\my_uart_top.root_partition.cmp.hdbx
....\...........\...................\my_uart_top.root_partition.cmp.kpt
....\...........\...................\my_uart_top.root_partition.cmp.logdb
....\...........\...................\my_uart_top.root_partition.cmp.rcf
....\...........\...................\my_uart_top.root_partition.map.atm
....\...........\...................\my_uart_top.root_partition.map.dpi
....\...........\...................\my_uart_top.root_partition.map.hdbx
....\...........\...................\my_uart_top.root_partition.map.kpt
....\...........\README
....\simulation\modelsim\modelsim.ini
....\..........\........\msim_transcript
....\..........\........\my_uart_top_run_msim_rtl_verilog.do
....\..........\........\my_uart_top_run_msim_rtl_verilog.do.bak
....\..........\........\rtl_work\my_uart_rx\verilog.psm
....\..........\........\........\..........\_primary.dat
....\..........\........\........\..........\_primary.dbs
....\..........\........\........\..........\_primary.vhd
....\..........\........\........\........top\verilog.psm
....\..........\........\........\...........\_primary.dat
....\..........\........\........\...........\_primary.dbs
....\..........\........\........\...........\_primary.vhd
....\..........\........\........\.........x\verilog.psm
....\..........\........\........\..........\_primary.dat
....\..........\........\........\..........\_primary.dbs
....\..........\........\........\..........\_primary.vhd
....\..........\........\........\speed_select\verilog.psm
....\..........\........\........\............\_primary.dat
....\..........\........\........\............\_primary.dbs
....\..........\........\........\............\_primary.vhd
....\..........\........\........\_info
....\..........\........\........\_vmake
....\speedselect.v
....\uart_rx.v
....\uart_top.asm.rpt
....\uart_top.done
....\uart_top.fit.rpt
....\uart_top.fit.summary
....\uart_top.flow.rpt
....\uart_top.map.rpt
....\uart_top.map.summary
....\uart_top.pin
....\uart_top.pof
....\uart_top.qpf
....\uart_top.qsf
....\uart_top.qws
....\uart_top.sof
....\uart_top.tan.rpt
....\uart_top.v
....\uart_top_nativelink_simulation.rpt
....\uart_tx.v
....\simulation\modelsim\rtl_work\my_uart_rx
....\..........\........\........\my_uart_top
....\..........\........\........\my_uart_tx
....\..........\........\........\speed_select
....\..........\........\........\_temp