文件名称:81
介绍说明－－下载内容均来自于网络，请自行研究使用
一个关于ＪＰＥＧ的例子，是用Verilog编写的，可以综合。-A case of JPEG is written in Verilog, can be integrated.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
81电路(是Verilog编写的 可以综合 很有实用价值)\djpeg\CVS\Entries
.............................................\.....\...\Repository
.............................................\.....\...\Root
.............................................\.....\c_model\CVS\Entries
.............................................\.....\.......\...\Repository
.............................................\.....\.......\...\Root
.............................................\.....\.......\djpeg.c
.............................................\.....\docs\CVS\Entries
.............................................\.....\....\...\Repository
.............................................\.....\....\...\Root
.............................................\.....\image\CVS\Entries
.............................................\.....\.....\...\Repository
.............................................\.....\.....\...\Root
.............................................\.....\.....\test.jpg
.............................................\.....\readme.txt
.............................................\.....\src\CVS\Entries
.............................................\.....\...\...\Repository
.............................................\.....\...\...\Root
.............................................\.....\...\jpeg_decode.v
.............................................\.....\...\jpeg_decode_fsm.v
.............................................\.....\...\jpeg_dht.v
.............................................\.....\...\jpeg_dqt.v
.............................................\.....\...\jpeg_haffuman.v
.............................................\.....\...\jpeg_hm_decode.v
.............................................\.....\...\jpeg_idct.v
.............................................\.....\...\jpeg_idctb.v
.............................................\.....\...\jpeg_idctx.v
.............................................\.....\...\jpeg_idcty.v
.............................................\.....\...\jpeg_regdata.v
.............................................\.....\...\jpeg_ycbcr.v
.............................................\.....\...\jpeg_ycbcr2rgb.v
.............................................\.....\...\jpeg_ycbcr_mem.v
.............................................\.....\...\jpeg_ziguzagu.v
.............................................\.....\...\jpeg_ziguzagu_reg.v
.............................................\.....\testbench\convbtoh
.............................................\.....\.........\convbtoh.c
.............................................\.....\.........\convsim
.............................................\.....\.........\convsim.c
.............................................\.....\.........\CVS\Entries
.............................................\.....\.........\...\Repository
.............................................\.....\.........\...\Root
.............................................\.....\.........\jpeg_test.v
.............................................\.....\.........\run.ms
.............................................\使用说明请参看右侧注释====〉〉.txt
.............................................\djpeg\c_model\CVS
.............................................\.....\docs\CVS
.............................................\.....\image\CVS
.............................................\.....\src\CVS
.............................................\.....\testbench\CVS
.............................................\.....\CVS
.............................................\.....\c_model
.............................................\.....\docs
.............................................\.....\image
.............................................\.....\src
.............................................\.....\testbench
.............................................\djpeg
81电路(是Verilog编写的 可以综合 很有实用价值)
.............................................\.....\...\Repository
.............................................\.....\...\Root
.............................................\.....\c_model\CVS\Entries
.............................................\.....\.......\...\Repository
.............................................\.....\.......\...\Root
.............................................\.....\.......\djpeg.c
.............................................\.....\docs\CVS\Entries
.............................................\.....\....\...\Repository
.............................................\.....\....\...\Root
.............................................\.....\image\CVS\Entries
.............................................\.....\.....\...\Repository
.............................................\.....\.....\...\Root
.............................................\.....\.....\test.jpg
.............................................\.....\readme.txt
.............................................\.....\src\CVS\Entries
.............................................\.....\...\...\Repository
.............................................\.....\...\...\Root
.............................................\.....\...\jpeg_decode.v
.............................................\.....\...\jpeg_decode_fsm.v
.............................................\.....\...\jpeg_dht.v
.............................................\.....\...\jpeg_dqt.v
.............................................\.....\...\jpeg_haffuman.v
.............................................\.....\...\jpeg_hm_decode.v
.............................................\.....\...\jpeg_idct.v
.............................................\.....\...\jpeg_idctb.v
.............................................\.....\...\jpeg_idctx.v
.............................................\.....\...\jpeg_idcty.v
.............................................\.....\...\jpeg_regdata.v
.............................................\.....\...\jpeg_ycbcr.v
.............................................\.....\...\jpeg_ycbcr2rgb.v
.............................................\.....\...\jpeg_ycbcr_mem.v
.............................................\.....\...\jpeg_ziguzagu.v
.............................................\.....\...\jpeg_ziguzagu_reg.v
.............................................\.....\testbench\convbtoh
.............................................\.....\.........\convbtoh.c
.............................................\.....\.........\convsim
.............................................\.....\.........\convsim.c
.............................................\.....\.........\CVS\Entries
.............................................\.....\.........\...\Repository
.............................................\.....\.........\...\Root
.............................................\.....\.........\jpeg_test.v
.............................................\.....\.........\run.ms
.............................................\使用说明请参看右侧注释====〉〉.txt
.............................................\djpeg\c_model\CVS
.............................................\.....\docs\CVS
.............................................\.....\image\CVS
.............................................\.....\src\CVS
.............................................\.....\testbench\CVS
.............................................\.....\CVS
.............................................\.....\c_model
.............................................\.....\docs
.............................................\.....\image
.............................................\.....\src
.............................................\.....\testbench
.............................................\djpeg
81电路(是Verilog编写的 可以综合 很有实用价值)