文件名称:odd_div

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 336kb
  • 下载次数:
  • 1次
  • 提 供 者:
  • 吴*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

利用Verilog实现奇术次分频,这里只举了一个例子,但任意奇数次分频均可以用该原理实现。-Patients achieving the odd times using Verilog frequency, just to cite one example, but any odd frequency can be achieved with the principle.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

odd_div\.cxl.mti_se.version

.......\compxlib.cfg

.......\compxlib.log

.......\modelsim.ini

.......\odd_div.cmd_log

.......\odd_div.gise

.......\odd_div.ise

.......\odd_div.lso

.......\odd_div.ngc

.......\odd_div.ngr

.......\odd_div.ntrc_log

.......\odd_div.prj

.......\odd_div.stx

.......\odd_div.syr

.......\odd_div.udo

.......\odd_div.v

.......\odd_div.xise

.......\odd_div.xst

.......\odd_div_summary.html

.......\odd_div_wave.fdo

.......\........xdb\tmp\ise\version

.......\...........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject

.......\...........\...\...\............\..................\.........\HDProject_StrTbl

.......\...........\...\...\............\..................\__stored_object_table__

.......\...........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl

.......\...........\...\...\............\.........\.......\RunOnce_tcl_StrTbl

.......\...........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main

.......\...........\...\...\............\................\................\dpm_project_main_StrTbl

.......\...........\...\...\............\................Gui\CSourceProcessView

.......\...........\...\...\............\...................\CSourceProcessView_StrTbl

.......\...........\...\...\............\...................\CViewSelector

.......\...........\...\...\............\...................\CViewSelector_StrTbl

.......\...........\...\...\............\...................\File-SynthesisOnly

.......\...........\...\...\............\...................\File-SynthesisOnly_StrTbl

.......\...........\...\...\............\...................\Library-SynthesisOnly

.......\...........\...\...\............\...................\Library-SynthesisOnly_StrTbl

.......\...........\...\...\............\...................\Process-BehavioralSim-

.......\...........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG

.......\...........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl

.......\...........\...\...\............\...................\Process-BehavioralSim-_StrTbl

.......\...........\...\...\............\...................\Process-SynthesisOnly-

.......\...........\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG

.......\...........\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl

.......\...........\...\...\............\...................\Process-SynthesisOnly-_StrTbl

.......\...........\...\...\............\...................\Source-BehavioralSim-AutoCompile

.......\...........\...\...\............\...................\Source-BehavioralSim-AutoCompile_StrTbl

.......\...........\...\...\............\...................\Source-SynthesisOnly-AutoCompile

.......\...........\...\...\............\...................\Source-SynthesisOnly-AutoCompile_StrTbl

.......\...........\...\...\............\xreport\Gc_RvReportViewer-Current-Module

.......\...........\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl

.......\...........\...\...\............\.......\Gc_RvReportViewer-Module-Data-odd_div

.......\...........\...\...\............\.......\Gc_RvReportViewer-Module-Data-odd_div_StrTbl

.......\...........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default

.......\...........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl

.......\...........\...\...\..REGISTRY__\Autonym\regkeys

.......\...........\...\...\............\bitgen\regkeys

.......\...........\...\...\............\...init\regkeys

.......\...........\...\...\............\common\regkeys

.......\...........\...\...\............\.pldfit\regkeys

.......\...........\...\...\............\dumpngdio\regkeys

.......\...........\...\...\............\fuse\regkeys

.......\...........\...\...\............\HierarchicalDesign\HDProject\regkeys

.......\...........\...\...\............\..................\regkeys

.......\...........\...\...\............\hprep6\regkeys

.......\...........\...\...\............\idem\regkeys

.......\...........\...\...\..

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